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![Amit Daniel Kachhap](/assets/img/avatar_default.png)
The existing comment about steppable hint instruction is not complete and only describes NOP instructions as steppable. As the function aarch64_insn_is_steppable_hint allows all white-listed instruction to be probed so the comment is updated to reflect this. Signed-off-by: Amit Daniel Kachhap <amit.kachhap@arm.com> Reviewed-by: Dave Martin <dave.martin@arm.com> Link: https://lore.kernel.org/r/20200914083656.21428-7-amit.kachhap@arm.com Signed-off-by: Will Deacon <will@kernel.org>
168 lines
5 KiB
C
168 lines
5 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* arch/arm64/kernel/probes/decode-insn.c
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*
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* Copyright (C) 2013 Linaro Limited.
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*/
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#include <linux/kernel.h>
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#include <linux/kprobes.h>
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#include <linux/module.h>
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#include <linux/kallsyms.h>
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#include <asm/insn.h>
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#include <asm/sections.h>
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#include "decode-insn.h"
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#include "simulate-insn.h"
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static bool __kprobes aarch64_insn_is_steppable(u32 insn)
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{
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/*
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* Branch instructions will write a new value into the PC which is
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* likely to be relative to the XOL address and therefore invalid.
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* Deliberate generation of an exception during stepping is also not
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* currently safe. Lastly, MSR instructions can do any number of nasty
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* things we can't handle during single-stepping.
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*/
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if (aarch64_get_insn_class(insn) == AARCH64_INSN_CLS_BR_SYS) {
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if (aarch64_insn_is_branch(insn) ||
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aarch64_insn_is_msr_imm(insn) ||
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aarch64_insn_is_msr_reg(insn) ||
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aarch64_insn_is_exception(insn) ||
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aarch64_insn_is_eret(insn) ||
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aarch64_insn_is_eret_auth(insn))
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return false;
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/*
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* The MRS instruction may not return a correct value when
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* executing in the single-stepping environment. We do make one
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* exception, for reading the DAIF bits.
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*/
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if (aarch64_insn_is_mrs(insn))
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return aarch64_insn_extract_system_reg(insn)
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!= AARCH64_INSN_SPCLREG_DAIF;
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/*
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* The HINT instruction is steppable only if it is in whitelist
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* and the rest of other such instructions are blocked for
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* single stepping as they may cause exception or other
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* unintended behaviour.
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*/
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if (aarch64_insn_is_hint(insn))
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return aarch64_insn_is_steppable_hint(insn);
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return true;
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}
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/*
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* Instructions which load PC relative literals are not going to work
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* when executed from an XOL slot. Instructions doing an exclusive
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* load/store are not going to complete successfully when single-step
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* exception handling happens in the middle of the sequence.
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*/
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if (aarch64_insn_uses_literal(insn) ||
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aarch64_insn_is_exclusive(insn))
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return false;
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return true;
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}
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/* Return:
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* INSN_REJECTED If instruction is one not allowed to kprobe,
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* INSN_GOOD If instruction is supported and uses instruction slot,
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* INSN_GOOD_NO_SLOT If instruction is supported but doesn't use its slot.
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*/
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enum probe_insn __kprobes
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arm_probe_decode_insn(probe_opcode_t insn, struct arch_probe_insn *api)
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{
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/*
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* Instructions reading or modifying the PC won't work from the XOL
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* slot.
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*/
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if (aarch64_insn_is_steppable(insn))
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return INSN_GOOD;
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if (aarch64_insn_is_bcond(insn)) {
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api->handler = simulate_b_cond;
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} else if (aarch64_insn_is_cbz(insn) ||
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aarch64_insn_is_cbnz(insn)) {
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api->handler = simulate_cbz_cbnz;
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} else if (aarch64_insn_is_tbz(insn) ||
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aarch64_insn_is_tbnz(insn)) {
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api->handler = simulate_tbz_tbnz;
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} else if (aarch64_insn_is_adr_adrp(insn)) {
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api->handler = simulate_adr_adrp;
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} else if (aarch64_insn_is_b(insn) ||
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aarch64_insn_is_bl(insn)) {
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api->handler = simulate_b_bl;
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} else if (aarch64_insn_is_br(insn) ||
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aarch64_insn_is_blr(insn) ||
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aarch64_insn_is_ret(insn)) {
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api->handler = simulate_br_blr_ret;
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} else if (aarch64_insn_is_ldr_lit(insn)) {
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api->handler = simulate_ldr_literal;
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} else if (aarch64_insn_is_ldrsw_lit(insn)) {
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api->handler = simulate_ldrsw_literal;
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} else {
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/*
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* Instruction cannot be stepped out-of-line and we don't
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* (yet) simulate it.
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*/
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return INSN_REJECTED;
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}
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return INSN_GOOD_NO_SLOT;
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}
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#ifdef CONFIG_KPROBES
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static bool __kprobes
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is_probed_address_atomic(kprobe_opcode_t *scan_start, kprobe_opcode_t *scan_end)
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{
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while (scan_start >= scan_end) {
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/*
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* atomic region starts from exclusive load and ends with
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* exclusive store.
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*/
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if (aarch64_insn_is_store_ex(le32_to_cpu(*scan_start)))
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return false;
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else if (aarch64_insn_is_load_ex(le32_to_cpu(*scan_start)))
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return true;
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scan_start--;
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}
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return false;
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}
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enum probe_insn __kprobes
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arm_kprobe_decode_insn(kprobe_opcode_t *addr, struct arch_specific_insn *asi)
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{
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enum probe_insn decoded;
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probe_opcode_t insn = le32_to_cpu(*addr);
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probe_opcode_t *scan_end = NULL;
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unsigned long size = 0, offset = 0;
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/*
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* If there's a symbol defined in front of and near enough to
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* the probe address assume it is the entry point to this
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* code and use it to further limit how far back we search
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* when determining if we're in an atomic sequence. If we could
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* not find any symbol skip the atomic test altogether as we
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* could otherwise end up searching irrelevant text/literals.
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* KPROBES depends on KALLSYMS so this last case should never
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* happen.
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*/
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if (kallsyms_lookup_size_offset((unsigned long) addr, &size, &offset)) {
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if (offset < (MAX_ATOMIC_CONTEXT_SIZE*sizeof(kprobe_opcode_t)))
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scan_end = addr - (offset / sizeof(kprobe_opcode_t));
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else
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scan_end = addr - MAX_ATOMIC_CONTEXT_SIZE;
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}
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decoded = arm_probe_decode_insn(insn, &asi->api);
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if (decoded != INSN_REJECTED && scan_end)
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if (is_probed_address_atomic(addr - 1, scan_end))
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return INSN_REJECTED;
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return decoded;
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}
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#endif
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