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7a110b9107
Re-factor master clock driver by splitting it into 2 clocks: prescaller and divider clocks. Based on registered clock flags the prescaler's rate could be changed at runtime. This is necessary for platforms supporting DVFS (e.g. SAMA7G5) where master clock could be changed at run-time. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Link: https://lore.kernel.org/r/1605800597-16720-11-git-send-email-claudiu.beznea@microchip.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
259 lines
7.8 KiB
C
259 lines
7.8 KiB
C
/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* drivers/clk/at91/pmc.h
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*
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* Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>
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*/
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#ifndef __PMC_H_
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#define __PMC_H_
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#include <linux/io.h>
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#include <linux/irqdomain.h>
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#include <linux/regmap.h>
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#include <linux/spinlock.h>
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extern spinlock_t pmc_pcr_lock;
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struct pmc_data {
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unsigned int ncore;
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struct clk_hw **chws;
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unsigned int nsystem;
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struct clk_hw **shws;
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unsigned int nperiph;
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struct clk_hw **phws;
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unsigned int ngck;
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struct clk_hw **ghws;
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unsigned int npck;
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struct clk_hw **pchws;
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struct clk_hw *hwtable[];
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};
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struct clk_range {
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unsigned long min;
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unsigned long max;
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};
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#define CLK_RANGE(MIN, MAX) {.min = MIN, .max = MAX,}
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struct clk_master_layout {
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u32 offset;
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u32 mask;
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u8 pres_shift;
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};
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extern const struct clk_master_layout at91rm9200_master_layout;
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extern const struct clk_master_layout at91sam9x5_master_layout;
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struct clk_master_characteristics {
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struct clk_range output;
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u32 divisors[5];
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u8 have_div3_pres;
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};
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struct clk_pll_layout {
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u32 pllr_mask;
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u32 mul_mask;
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u32 frac_mask;
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u32 div_mask;
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u32 endiv_mask;
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u8 mul_shift;
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u8 frac_shift;
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u8 div_shift;
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u8 endiv_shift;
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};
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extern const struct clk_pll_layout at91rm9200_pll_layout;
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extern const struct clk_pll_layout at91sam9g45_pll_layout;
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extern const struct clk_pll_layout at91sam9g20_pllb_layout;
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extern const struct clk_pll_layout sama5d3_pll_layout;
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struct clk_pll_characteristics {
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struct clk_range input;
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int num_output;
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const struct clk_range *output;
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u16 *icpll;
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u8 *out;
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u8 upll : 1;
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};
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struct clk_programmable_layout {
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u8 pres_mask;
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u8 pres_shift;
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u8 css_mask;
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u8 have_slck_mck;
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u8 is_pres_direct;
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};
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extern const struct clk_programmable_layout at91rm9200_programmable_layout;
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extern const struct clk_programmable_layout at91sam9g45_programmable_layout;
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extern const struct clk_programmable_layout at91sam9x5_programmable_layout;
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struct clk_pcr_layout {
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u32 offset;
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u32 cmd;
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u32 div_mask;
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u32 gckcss_mask;
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u32 pid_mask;
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};
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#define field_get(_mask, _reg) (((_reg) & (_mask)) >> (ffs(_mask) - 1))
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#define field_prep(_mask, _val) (((_val) << (ffs(_mask) - 1)) & (_mask))
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#define ndck(a, s) (a[s - 1].id + 1)
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#define nck(a) (a[ARRAY_SIZE(a) - 1].id + 1)
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struct pmc_data *pmc_data_allocate(unsigned int ncore, unsigned int nsystem,
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unsigned int nperiph, unsigned int ngck,
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unsigned int npck);
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int of_at91_get_clk_range(struct device_node *np, const char *propname,
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struct clk_range *range);
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struct clk_hw *of_clk_hw_pmc_get(struct of_phandle_args *clkspec, void *data);
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struct clk_hw * __init
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at91_clk_register_audio_pll_frac(struct regmap *regmap, const char *name,
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const char *parent_name);
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struct clk_hw * __init
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at91_clk_register_audio_pll_pad(struct regmap *regmap, const char *name,
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const char *parent_name);
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struct clk_hw * __init
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at91_clk_register_audio_pll_pmc(struct regmap *regmap, const char *name,
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const char *parent_name);
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struct clk_hw * __init
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at91_clk_register_generated(struct regmap *regmap, spinlock_t *lock,
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const struct clk_pcr_layout *layout,
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const char *name, const char **parent_names,
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u32 *mux_table, u8 num_parents, u8 id,
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const struct clk_range *range, int chg_pid);
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struct clk_hw * __init
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at91_clk_register_h32mx(struct regmap *regmap, const char *name,
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const char *parent_name);
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struct clk_hw * __init
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at91_clk_i2s_mux_register(struct regmap *regmap, const char *name,
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const char * const *parent_names,
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unsigned int num_parents, u8 bus_id);
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struct clk_hw * __init
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at91_clk_register_main_rc_osc(struct regmap *regmap, const char *name,
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u32 frequency, u32 accuracy);
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struct clk_hw * __init
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at91_clk_register_main_osc(struct regmap *regmap, const char *name,
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const char *parent_name, bool bypass);
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struct clk_hw * __init
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at91_clk_register_rm9200_main(struct regmap *regmap,
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const char *name,
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const char *parent_name);
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struct clk_hw * __init
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at91_clk_register_sam9x5_main(struct regmap *regmap, const char *name,
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const char **parent_names, int num_parents);
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struct clk_hw * __init
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at91_clk_register_master_pres(struct regmap *regmap, const char *name,
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int num_parents, const char **parent_names,
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const struct clk_master_layout *layout,
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const struct clk_master_characteristics *characteristics,
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spinlock_t *lock, u32 flags, int chg_pid);
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struct clk_hw * __init
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at91_clk_register_master_div(struct regmap *regmap, const char *name,
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const char *parent_names,
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const struct clk_master_layout *layout,
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const struct clk_master_characteristics *characteristics,
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spinlock_t *lock, u32 flags);
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struct clk_hw * __init
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at91_clk_sama7g5_register_master(struct regmap *regmap,
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const char *name, int num_parents,
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const char **parent_names, u32 *mux_table,
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spinlock_t *lock, u8 id, bool critical,
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int chg_pid);
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struct clk_hw * __init
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at91_clk_register_peripheral(struct regmap *regmap, const char *name,
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const char *parent_name, u32 id);
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struct clk_hw * __init
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at91_clk_register_sam9x5_peripheral(struct regmap *regmap, spinlock_t *lock,
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const struct clk_pcr_layout *layout,
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const char *name, const char *parent_name,
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u32 id, const struct clk_range *range,
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int chg_pid);
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struct clk_hw * __init
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at91_clk_register_pll(struct regmap *regmap, const char *name,
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const char *parent_name, u8 id,
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const struct clk_pll_layout *layout,
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const struct clk_pll_characteristics *characteristics);
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struct clk_hw * __init
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at91_clk_register_plldiv(struct regmap *regmap, const char *name,
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const char *parent_name);
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struct clk_hw * __init
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sam9x60_clk_register_div_pll(struct regmap *regmap, spinlock_t *lock,
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const char *name, const char *parent_name, u8 id,
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const struct clk_pll_characteristics *characteristics,
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const struct clk_pll_layout *layout, u32 flags);
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struct clk_hw * __init
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sam9x60_clk_register_frac_pll(struct regmap *regmap, spinlock_t *lock,
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const char *name, const char *parent_name,
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struct clk_hw *parent_hw, u8 id,
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const struct clk_pll_characteristics *characteristics,
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const struct clk_pll_layout *layout, u32 flags);
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struct clk_hw * __init
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at91_clk_register_programmable(struct regmap *regmap, const char *name,
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const char **parent_names, u8 num_parents, u8 id,
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const struct clk_programmable_layout *layout,
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u32 *mux_table);
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struct clk_hw * __init
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at91_clk_register_sam9260_slow(struct regmap *regmap,
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const char *name,
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const char **parent_names,
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int num_parents);
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struct clk_hw * __init
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at91sam9x5_clk_register_smd(struct regmap *regmap, const char *name,
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const char **parent_names, u8 num_parents);
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struct clk_hw * __init
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at91_clk_register_system(struct regmap *regmap, const char *name,
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const char *parent_name, u8 id);
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struct clk_hw * __init
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at91sam9x5_clk_register_usb(struct regmap *regmap, const char *name,
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const char **parent_names, u8 num_parents);
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struct clk_hw * __init
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at91sam9n12_clk_register_usb(struct regmap *regmap, const char *name,
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const char *parent_name);
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struct clk_hw * __init
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sam9x60_clk_register_usb(struct regmap *regmap, const char *name,
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const char **parent_names, u8 num_parents);
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struct clk_hw * __init
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at91rm9200_clk_register_usb(struct regmap *regmap, const char *name,
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const char *parent_name, const u32 *divisors);
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struct clk_hw * __init
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at91_clk_register_utmi(struct regmap *regmap_pmc, struct regmap *regmap_sfr,
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const char *name, const char *parent_name);
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struct clk_hw * __init
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at91_clk_sama7g5_register_utmi(struct regmap *regmap, const char *name,
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const char *parent_name);
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#ifdef CONFIG_PM
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void pmc_register_id(u8 id);
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void pmc_register_pck(u8 pck);
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#else
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static inline void pmc_register_id(u8 id) {}
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static inline void pmc_register_pck(u8 pck) {}
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#endif
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#endif /* __PMC_H_ */
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