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Based on 1 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of the gnu general public license as published by the free software foundation either version 2 of the license or at your option any later version extracted by the scancode license scanner the SPDX license identifier GPL-2.0-or-later has been chosen to replace the boilerplate/reference in 3029 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Allison Randal <allison@lohutok.net> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190527070032.746973796@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
145 lines
4.7 KiB
C
145 lines
4.7 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* Cirrus Logic CLPS711X CLK driver
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*
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* Copyright (C) 2014 Alexander Shiyan <shc_work@mail.ru>
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*/
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#include <linux/clk-provider.h>
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#include <linux/clkdev.h>
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#include <linux/io.h>
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#include <linux/ioport.h>
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#include <linux/of_address.h>
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#include <linux/slab.h>
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#include <linux/mfd/syscon/clps711x.h>
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#include <dt-bindings/clock/clps711x-clock.h>
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#define CLPS711X_SYSCON1 (0x0100)
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#define CLPS711X_SYSCON2 (0x1100)
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#define CLPS711X_SYSFLG2 (CLPS711X_SYSCON2 + SYSFLG_OFFSET)
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#define CLPS711X_PLLR (0xa5a8)
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#define CLPS711X_EXT_FREQ (13000000)
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#define CLPS711X_OSC_FREQ (3686400)
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static const struct clk_div_table spi_div_table[] = {
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{ .val = 0, .div = 32, },
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{ .val = 1, .div = 8, },
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{ .val = 2, .div = 2, },
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{ .val = 3, .div = 1, },
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};
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static const struct clk_div_table timer_div_table[] = {
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{ .val = 0, .div = 256, },
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{ .val = 1, .div = 1, },
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};
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struct clps711x_clk {
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spinlock_t lock;
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struct clk_hw_onecell_data clk_data;
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};
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static void __init clps711x_clk_init_dt(struct device_node *np)
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{
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u32 tmp, f_cpu, f_pll, f_bus, f_tim, f_pwm, f_spi, fref = 0;
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struct clps711x_clk *clps711x_clk;
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void __iomem *base;
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WARN_ON(of_property_read_u32(np, "startup-frequency", &fref));
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base = of_iomap(np, 0);
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BUG_ON(!base);
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clps711x_clk = kzalloc(struct_size(clps711x_clk, clk_data.hws,
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CLPS711X_CLK_MAX),
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GFP_KERNEL);
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BUG_ON(!clps711x_clk);
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spin_lock_init(&clps711x_clk->lock);
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/* Read PLL multiplier value and sanity check */
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tmp = readl(base + CLPS711X_PLLR) >> 24;
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if (((tmp >= 10) && (tmp <= 50)) || !fref)
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f_pll = DIV_ROUND_UP(CLPS711X_OSC_FREQ * tmp, 2);
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else
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f_pll = fref;
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tmp = readl(base + CLPS711X_SYSFLG2);
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if (tmp & SYSFLG2_CKMODE) {
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f_cpu = CLPS711X_EXT_FREQ;
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f_bus = CLPS711X_EXT_FREQ;
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f_spi = DIV_ROUND_CLOSEST(CLPS711X_EXT_FREQ, 96);
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f_pll = 0;
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f_pwm = DIV_ROUND_CLOSEST(CLPS711X_EXT_FREQ, 128);
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} else {
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f_cpu = f_pll;
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if (f_cpu > 36864000)
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f_bus = DIV_ROUND_UP(f_cpu, 2);
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else
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f_bus = 36864000 / 2;
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f_spi = DIV_ROUND_CLOSEST(f_cpu, 576);
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f_pwm = DIV_ROUND_CLOSEST(f_cpu, 768);
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}
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if (tmp & SYSFLG2_CKMODE) {
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if (readl(base + CLPS711X_SYSCON2) & SYSCON2_OSTB)
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f_tim = DIV_ROUND_CLOSEST(CLPS711X_EXT_FREQ, 26);
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else
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f_tim = DIV_ROUND_CLOSEST(CLPS711X_EXT_FREQ, 24);
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} else
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f_tim = DIV_ROUND_CLOSEST(f_cpu, 144);
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tmp = readl(base + CLPS711X_SYSCON1);
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/* Timer1 in free running mode.
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* Counter will wrap around to 0xffff when it underflows
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* and will continue to count down.
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*/
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tmp &= ~(SYSCON1_TC1M | SYSCON1_TC1S);
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/* Timer2 in prescale mode.
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* Value writen is automatically re-loaded when
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* the counter underflows.
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*/
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tmp |= SYSCON1_TC2M | SYSCON1_TC2S;
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writel(tmp, base + CLPS711X_SYSCON1);
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clps711x_clk->clk_data.hws[CLPS711X_CLK_DUMMY] =
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clk_hw_register_fixed_rate(NULL, "dummy", NULL, 0, 0);
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clps711x_clk->clk_data.hws[CLPS711X_CLK_CPU] =
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clk_hw_register_fixed_rate(NULL, "cpu", NULL, 0, f_cpu);
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clps711x_clk->clk_data.hws[CLPS711X_CLK_BUS] =
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clk_hw_register_fixed_rate(NULL, "bus", NULL, 0, f_bus);
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clps711x_clk->clk_data.hws[CLPS711X_CLK_PLL] =
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clk_hw_register_fixed_rate(NULL, "pll", NULL, 0, f_pll);
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clps711x_clk->clk_data.hws[CLPS711X_CLK_TIMERREF] =
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clk_hw_register_fixed_rate(NULL, "timer_ref", NULL, 0, f_tim);
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clps711x_clk->clk_data.hws[CLPS711X_CLK_TIMER1] =
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clk_hw_register_divider_table(NULL, "timer1", "timer_ref", 0,
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base + CLPS711X_SYSCON1, 5, 1, 0,
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timer_div_table, &clps711x_clk->lock);
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clps711x_clk->clk_data.hws[CLPS711X_CLK_TIMER2] =
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clk_hw_register_divider_table(NULL, "timer2", "timer_ref", 0,
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base + CLPS711X_SYSCON1, 7, 1, 0,
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timer_div_table, &clps711x_clk->lock);
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clps711x_clk->clk_data.hws[CLPS711X_CLK_PWM] =
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clk_hw_register_fixed_rate(NULL, "pwm", NULL, 0, f_pwm);
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clps711x_clk->clk_data.hws[CLPS711X_CLK_SPIREF] =
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clk_hw_register_fixed_rate(NULL, "spi_ref", NULL, 0, f_spi);
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clps711x_clk->clk_data.hws[CLPS711X_CLK_SPI] =
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clk_hw_register_divider_table(NULL, "spi", "spi_ref", 0,
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base + CLPS711X_SYSCON1, 16, 2, 0,
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spi_div_table, &clps711x_clk->lock);
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clps711x_clk->clk_data.hws[CLPS711X_CLK_UART] =
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clk_hw_register_fixed_factor(NULL, "uart", "bus", 0, 1, 10);
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clps711x_clk->clk_data.hws[CLPS711X_CLK_TICK] =
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clk_hw_register_fixed_rate(NULL, "tick", NULL, 0, 64);
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for (tmp = 0; tmp < CLPS711X_CLK_MAX; tmp++)
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if (IS_ERR(clps711x_clk->clk_data.hws[tmp]))
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pr_err("clk %i: register failed with %ld\n",
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tmp, PTR_ERR(clps711x_clk->clk_data.hws[tmp]));
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clps711x_clk->clk_data.num = CLPS711X_CLK_MAX;
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of_clk_add_hw_provider(np, of_clk_hw_onecell_get,
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&clps711x_clk->clk_data);
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}
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CLK_OF_DECLARE(clps711x, "cirrus,ep7209-clk", clps711x_clk_init_dt);
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