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![Randy Dunlap](/assets/img/avatar_default.png)
Use the 'fallthrough' macro to document that this switch case
does indeed fall through to the next case.
../drivers/irqchip/irq-tb10x.c: In function 'tb10x_irq_set_type':
../drivers/irqchip/irq-tb10x.c:62:13: warning: this statement may fall through [-Wimplicit-fallthrough=]
62 | flow_type = IRQ_TYPE_LEVEL_LOW;
../drivers/irqchip/irq-tb10x.c:63:2: note: here
63 | case IRQ_TYPE_LEVEL_LOW:
| ^~~~
Fixes: b06eb0173e
("irqchip: Add TB10x interrupt controller driver")
Signed-off-by: Randy Dunlap <rdunlap@infradead.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Marc Zyngier <maz@kernel.org>
Cc: Christian Ruppert <christian.ruppert@abilis.com>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20210422051620.23021-1-rdunlap@infradead.org
185 lines
4.9 KiB
C
185 lines
4.9 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Abilis Systems interrupt controller driver
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*
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* Copyright (C) Abilis Systems 2012
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*
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* Author: Christian Ruppert <christian.ruppert@abilis.com>
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*/
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#include <linux/interrupt.h>
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#include <linux/irqdomain.h>
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#include <linux/irq.h>
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#include <linux/irqchip.h>
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#include <linux/of_irq.h>
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#include <linux/of_address.h>
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#include <linux/of_platform.h>
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#include <linux/io.h>
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#include <linux/slab.h>
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#include <linux/bitops.h>
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#define AB_IRQCTL_INT_ENABLE 0x00
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#define AB_IRQCTL_INT_STATUS 0x04
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#define AB_IRQCTL_SRC_MODE 0x08
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#define AB_IRQCTL_SRC_POLARITY 0x0C
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#define AB_IRQCTL_INT_MODE 0x10
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#define AB_IRQCTL_INT_POLARITY 0x14
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#define AB_IRQCTL_INT_FORCE 0x18
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#define AB_IRQCTL_MAXIRQ 32
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static inline void ab_irqctl_writereg(struct irq_chip_generic *gc, u32 reg,
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u32 val)
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{
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irq_reg_writel(gc, val, reg);
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}
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static inline u32 ab_irqctl_readreg(struct irq_chip_generic *gc, u32 reg)
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{
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return irq_reg_readl(gc, reg);
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}
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static int tb10x_irq_set_type(struct irq_data *data, unsigned int flow_type)
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{
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struct irq_chip_generic *gc = irq_data_get_irq_chip_data(data);
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uint32_t im, mod, pol;
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im = data->mask;
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irq_gc_lock(gc);
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mod = ab_irqctl_readreg(gc, AB_IRQCTL_SRC_MODE) | im;
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pol = ab_irqctl_readreg(gc, AB_IRQCTL_SRC_POLARITY) | im;
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switch (flow_type & IRQF_TRIGGER_MASK) {
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case IRQ_TYPE_EDGE_FALLING:
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pol ^= im;
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break;
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case IRQ_TYPE_LEVEL_HIGH:
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mod ^= im;
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break;
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case IRQ_TYPE_NONE:
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flow_type = IRQ_TYPE_LEVEL_LOW;
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fallthrough;
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case IRQ_TYPE_LEVEL_LOW:
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mod ^= im;
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pol ^= im;
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break;
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case IRQ_TYPE_EDGE_RISING:
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break;
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default:
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irq_gc_unlock(gc);
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pr_err("%s: Cannot assign multiple trigger modes to IRQ %d.\n",
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__func__, data->irq);
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return -EBADR;
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}
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irqd_set_trigger_type(data, flow_type);
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irq_setup_alt_chip(data, flow_type);
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ab_irqctl_writereg(gc, AB_IRQCTL_SRC_MODE, mod);
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ab_irqctl_writereg(gc, AB_IRQCTL_SRC_POLARITY, pol);
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ab_irqctl_writereg(gc, AB_IRQCTL_INT_STATUS, im);
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irq_gc_unlock(gc);
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return IRQ_SET_MASK_OK;
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}
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static void tb10x_irq_cascade(struct irq_desc *desc)
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{
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struct irq_domain *domain = irq_desc_get_handler_data(desc);
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unsigned int irq = irq_desc_get_irq(desc);
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generic_handle_irq(irq_find_mapping(domain, irq));
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}
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static int __init of_tb10x_init_irq(struct device_node *ictl,
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struct device_node *parent)
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{
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int i, ret, nrirqs = of_irq_count(ictl);
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struct resource mem;
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struct irq_chip_generic *gc;
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struct irq_domain *domain;
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void __iomem *reg_base;
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if (of_address_to_resource(ictl, 0, &mem)) {
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pr_err("%pOFn: No registers declared in DeviceTree.\n",
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ictl);
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return -EINVAL;
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}
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if (!request_mem_region(mem.start, resource_size(&mem),
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ictl->full_name)) {
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pr_err("%pOFn: Request mem region failed.\n", ictl);
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return -EBUSY;
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}
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reg_base = ioremap(mem.start, resource_size(&mem));
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if (!reg_base) {
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ret = -EBUSY;
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pr_err("%pOFn: ioremap failed.\n", ictl);
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goto ioremap_fail;
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}
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domain = irq_domain_add_linear(ictl, AB_IRQCTL_MAXIRQ,
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&irq_generic_chip_ops, NULL);
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if (!domain) {
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ret = -ENOMEM;
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pr_err("%pOFn: Could not register interrupt domain.\n",
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ictl);
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goto irq_domain_add_fail;
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}
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ret = irq_alloc_domain_generic_chips(domain, AB_IRQCTL_MAXIRQ,
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2, ictl->name, handle_level_irq,
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IRQ_NOREQUEST, IRQ_NOPROBE,
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IRQ_GC_INIT_MASK_CACHE);
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if (ret) {
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pr_err("%pOFn: Could not allocate generic interrupt chip.\n",
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ictl);
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goto gc_alloc_fail;
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}
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gc = domain->gc->gc[0];
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gc->reg_base = reg_base;
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gc->chip_types[0].type = IRQ_TYPE_LEVEL_MASK;
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gc->chip_types[0].chip.irq_mask = irq_gc_mask_clr_bit;
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gc->chip_types[0].chip.irq_unmask = irq_gc_mask_set_bit;
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gc->chip_types[0].chip.irq_set_type = tb10x_irq_set_type;
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gc->chip_types[0].regs.mask = AB_IRQCTL_INT_ENABLE;
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gc->chip_types[1].type = IRQ_TYPE_EDGE_BOTH;
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gc->chip_types[1].chip.name = gc->chip_types[0].chip.name;
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gc->chip_types[1].chip.irq_ack = irq_gc_ack_set_bit;
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gc->chip_types[1].chip.irq_mask = irq_gc_mask_clr_bit;
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gc->chip_types[1].chip.irq_unmask = irq_gc_mask_set_bit;
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gc->chip_types[1].chip.irq_set_type = tb10x_irq_set_type;
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gc->chip_types[1].regs.ack = AB_IRQCTL_INT_STATUS;
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gc->chip_types[1].regs.mask = AB_IRQCTL_INT_ENABLE;
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gc->chip_types[1].handler = handle_edge_irq;
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for (i = 0; i < nrirqs; i++) {
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unsigned int irq = irq_of_parse_and_map(ictl, i);
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irq_set_chained_handler_and_data(irq, tb10x_irq_cascade,
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domain);
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}
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ab_irqctl_writereg(gc, AB_IRQCTL_INT_ENABLE, 0);
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ab_irqctl_writereg(gc, AB_IRQCTL_INT_MODE, 0);
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ab_irqctl_writereg(gc, AB_IRQCTL_INT_POLARITY, 0);
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ab_irqctl_writereg(gc, AB_IRQCTL_INT_STATUS, ~0UL);
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return 0;
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gc_alloc_fail:
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irq_domain_remove(domain);
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irq_domain_add_fail:
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iounmap(reg_base);
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ioremap_fail:
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release_mem_region(mem.start, resource_size(&mem));
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return ret;
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}
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IRQCHIP_DECLARE(tb10x_intc, "abilis,tb10x-ictl", of_tb10x_init_irq);
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