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![Sungbo Eo](/assets/img/avatar_default.png)
Clear its own IRQs before the parent IRQ get enabled, so that the
remaining IRQs do not accidentally interrupt the parent IRQ controller.
This patch also fixes a reboot bug on OX820 SoC, where the remaining
rps-timer IRQ raises a GIC interrupt that is left pending. After that,
the rps-timer IRQ is cleared during driver initialization, and there's
no IRQ left in rps-irq when local_irq_enable() is called, which evokes
an error message "unexpected IRQ trap".
Fixes: bdd272cbb9
("irqchip: versatile FPGA: support cascaded interrupts from DT")
Signed-off-by: Sungbo Eo <mans0n@gorani.run>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Cc: stable@vger.kernel.org
Link: https://lore.kernel.org/r/20200321133842.2408823-1-mans0n@gorani.run
240 lines
6.1 KiB
C
240 lines
6.1 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Support for Versatile FPGA-based IRQ controllers
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*/
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#include <linux/bitops.h>
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#include <linux/irq.h>
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#include <linux/io.h>
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#include <linux/irqchip.h>
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#include <linux/irqchip/chained_irq.h>
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#include <linux/irqchip/versatile-fpga.h>
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#include <linux/irqdomain.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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#include <asm/exception.h>
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#include <asm/mach/irq.h>
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#define IRQ_STATUS 0x00
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#define IRQ_RAW_STATUS 0x04
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#define IRQ_ENABLE_SET 0x08
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#define IRQ_ENABLE_CLEAR 0x0c
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#define INT_SOFT_SET 0x10
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#define INT_SOFT_CLEAR 0x14
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#define FIQ_STATUS 0x20
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#define FIQ_RAW_STATUS 0x24
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#define FIQ_ENABLE 0x28
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#define FIQ_ENABLE_SET 0x28
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#define FIQ_ENABLE_CLEAR 0x2C
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#define PIC_ENABLES 0x20 /* set interrupt pass through bits */
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/**
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* struct fpga_irq_data - irq data container for the FPGA IRQ controller
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* @base: memory offset in virtual memory
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* @chip: chip container for this instance
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* @domain: IRQ domain for this instance
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* @valid: mask for valid IRQs on this controller
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* @used_irqs: number of active IRQs on this controller
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*/
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struct fpga_irq_data {
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void __iomem *base;
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struct irq_chip chip;
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u32 valid;
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struct irq_domain *domain;
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u8 used_irqs;
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};
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/* we cannot allocate memory when the controllers are initially registered */
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static struct fpga_irq_data fpga_irq_devices[CONFIG_VERSATILE_FPGA_IRQ_NR];
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static int fpga_irq_id;
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static void fpga_irq_mask(struct irq_data *d)
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{
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struct fpga_irq_data *f = irq_data_get_irq_chip_data(d);
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u32 mask = 1 << d->hwirq;
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writel(mask, f->base + IRQ_ENABLE_CLEAR);
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}
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static void fpga_irq_unmask(struct irq_data *d)
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{
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struct fpga_irq_data *f = irq_data_get_irq_chip_data(d);
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u32 mask = 1 << d->hwirq;
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writel(mask, f->base + IRQ_ENABLE_SET);
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}
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static void fpga_irq_handle(struct irq_desc *desc)
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{
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struct irq_chip *chip = irq_desc_get_chip(desc);
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struct fpga_irq_data *f = irq_desc_get_handler_data(desc);
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u32 status;
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chained_irq_enter(chip, desc);
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status = readl(f->base + IRQ_STATUS);
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if (status == 0) {
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do_bad_IRQ(desc);
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goto out;
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}
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do {
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unsigned int irq = ffs(status) - 1;
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status &= ~(1 << irq);
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generic_handle_irq(irq_find_mapping(f->domain, irq));
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} while (status);
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out:
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chained_irq_exit(chip, desc);
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}
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/*
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* Handle each interrupt in a single FPGA IRQ controller. Returns non-zero
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* if we've handled at least one interrupt. This does a single read of the
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* status register and handles all interrupts in order from LSB first.
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*/
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static int handle_one_fpga(struct fpga_irq_data *f, struct pt_regs *regs)
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{
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int handled = 0;
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int irq;
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u32 status;
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while ((status = readl(f->base + IRQ_STATUS))) {
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irq = ffs(status) - 1;
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handle_domain_irq(f->domain, irq, regs);
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handled = 1;
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}
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return handled;
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}
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/*
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* Keep iterating over all registered FPGA IRQ controllers until there are
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* no pending interrupts.
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*/
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asmlinkage void __exception_irq_entry fpga_handle_irq(struct pt_regs *regs)
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{
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int i, handled;
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do {
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for (i = 0, handled = 0; i < fpga_irq_id; ++i)
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handled |= handle_one_fpga(&fpga_irq_devices[i], regs);
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} while (handled);
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}
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static int fpga_irqdomain_map(struct irq_domain *d, unsigned int irq,
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irq_hw_number_t hwirq)
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{
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struct fpga_irq_data *f = d->host_data;
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/* Skip invalid IRQs, only register handlers for the real ones */
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if (!(f->valid & BIT(hwirq)))
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return -EPERM;
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irq_set_chip_data(irq, f);
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irq_set_chip_and_handler(irq, &f->chip,
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handle_level_irq);
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irq_set_probe(irq);
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return 0;
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}
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static const struct irq_domain_ops fpga_irqdomain_ops = {
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.map = fpga_irqdomain_map,
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.xlate = irq_domain_xlate_onetwocell,
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};
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void __init fpga_irq_init(void __iomem *base, const char *name, int irq_start,
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int parent_irq, u32 valid, struct device_node *node)
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{
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struct fpga_irq_data *f;
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int i;
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if (fpga_irq_id >= ARRAY_SIZE(fpga_irq_devices)) {
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pr_err("%s: too few FPGA IRQ controllers, increase CONFIG_VERSATILE_FPGA_IRQ_NR\n", __func__);
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return;
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}
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f = &fpga_irq_devices[fpga_irq_id];
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f->base = base;
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f->chip.name = name;
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f->chip.irq_ack = fpga_irq_mask;
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f->chip.irq_mask = fpga_irq_mask;
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f->chip.irq_unmask = fpga_irq_unmask;
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f->valid = valid;
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if (parent_irq != -1) {
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irq_set_chained_handler_and_data(parent_irq, fpga_irq_handle,
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f);
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}
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/* This will also allocate irq descriptors */
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f->domain = irq_domain_add_simple(node, fls(valid), irq_start,
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&fpga_irqdomain_ops, f);
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/* This will allocate all valid descriptors in the linear case */
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for (i = 0; i < fls(valid); i++)
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if (valid & BIT(i)) {
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if (!irq_start)
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irq_create_mapping(f->domain, i);
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f->used_irqs++;
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}
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pr_info("FPGA IRQ chip %d \"%s\" @ %p, %u irqs",
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fpga_irq_id, name, base, f->used_irqs);
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if (parent_irq != -1)
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pr_cont(", parent IRQ: %d\n", parent_irq);
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else
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pr_cont("\n");
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fpga_irq_id++;
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}
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#ifdef CONFIG_OF
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int __init fpga_irq_of_init(struct device_node *node,
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struct device_node *parent)
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{
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void __iomem *base;
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u32 clear_mask;
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u32 valid_mask;
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int parent_irq;
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if (WARN_ON(!node))
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return -ENODEV;
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base = of_iomap(node, 0);
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WARN(!base, "unable to map fpga irq registers\n");
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if (of_property_read_u32(node, "clear-mask", &clear_mask))
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clear_mask = 0;
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if (of_property_read_u32(node, "valid-mask", &valid_mask))
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valid_mask = 0;
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writel(clear_mask, base + IRQ_ENABLE_CLEAR);
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writel(clear_mask, base + FIQ_ENABLE_CLEAR);
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/* Some chips are cascaded from a parent IRQ */
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parent_irq = irq_of_parse_and_map(node, 0);
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if (!parent_irq) {
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set_handle_irq(fpga_handle_irq);
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parent_irq = -1;
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}
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fpga_irq_init(base, node->name, 0, parent_irq, valid_mask, node);
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/*
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* On Versatile AB/PB, some secondary interrupts have a direct
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* pass-thru to the primary controller for IRQs 20 and 22-31 which need
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* to be enabled. See section 3.10 of the Versatile AB user guide.
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*/
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if (of_device_is_compatible(node, "arm,versatile-sic"))
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writel(0xffd00000, base + PIC_ENABLES);
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return 0;
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}
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IRQCHIP_DECLARE(arm_fpga, "arm,versatile-fpga-irq", fpga_irq_of_init);
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IRQCHIP_DECLARE(arm_fpga_sic, "arm,versatile-sic", fpga_irq_of_init);
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IRQCHIP_DECLARE(ox810se_rps, "oxsemi,ox810se-rps-irq", fpga_irq_of_init);
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#endif
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