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![Manivannan Sadhasivam](/assets/img/avatar_default.png)
In SDX55, the IPC bits are located in the APCS GCC block. Also, this block can provide clock functionality. Hence, add support for IPC with correct offset and name of the clock provider. Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
197 lines
5.4 KiB
C
197 lines
5.4 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) 2017, Linaro Ltd
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/io.h>
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#include <linux/slab.h>
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#include <linux/of.h>
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#include <linux/of_platform.h>
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#include <linux/platform_device.h>
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#include <linux/regmap.h>
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#include <linux/mailbox_controller.h>
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#define QCOM_APCS_IPC_BITS 32
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struct qcom_apcs_ipc {
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struct mbox_controller mbox;
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struct mbox_chan mbox_chans[QCOM_APCS_IPC_BITS];
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struct regmap *regmap;
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unsigned long offset;
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struct platform_device *clk;
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};
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struct qcom_apcs_ipc_data {
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int offset;
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char *clk_name;
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};
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static const struct qcom_apcs_ipc_data ipq6018_apcs_data = {
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.offset = 8, .clk_name = "qcom,apss-ipq6018-clk"
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};
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static const struct qcom_apcs_ipc_data ipq8074_apcs_data = {
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.offset = 8, .clk_name = NULL
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};
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static const struct qcom_apcs_ipc_data msm8916_apcs_data = {
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.offset = 8, .clk_name = "qcom-apcs-msm8916-clk"
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};
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static const struct qcom_apcs_ipc_data msm8994_apcs_data = {
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.offset = 8, .clk_name = NULL
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};
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static const struct qcom_apcs_ipc_data msm8996_apcs_data = {
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.offset = 16, .clk_name = NULL
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};
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static const struct qcom_apcs_ipc_data msm8998_apcs_data = {
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.offset = 8, .clk_name = NULL
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};
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static const struct qcom_apcs_ipc_data sdm660_apcs_data = {
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.offset = 8, .clk_name = NULL
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};
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static const struct qcom_apcs_ipc_data apps_shared_apcs_data = {
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.offset = 12, .clk_name = NULL
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};
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static const struct qcom_apcs_ipc_data sdx55_apcs_data = {
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.offset = 0x1008, .clk_name = "qcom-sdx55-acps-clk"
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};
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static const struct regmap_config apcs_regmap_config = {
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.reg_bits = 32,
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.reg_stride = 4,
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.val_bits = 32,
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.max_register = 0x1008,
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.fast_io = true,
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};
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static int qcom_apcs_ipc_send_data(struct mbox_chan *chan, void *data)
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{
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struct qcom_apcs_ipc *apcs = container_of(chan->mbox,
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struct qcom_apcs_ipc, mbox);
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unsigned long idx = (unsigned long)chan->con_priv;
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return regmap_write(apcs->regmap, apcs->offset, BIT(idx));
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}
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static const struct mbox_chan_ops qcom_apcs_ipc_ops = {
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.send_data = qcom_apcs_ipc_send_data,
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};
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static int qcom_apcs_ipc_probe(struct platform_device *pdev)
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{
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struct qcom_apcs_ipc *apcs;
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const struct qcom_apcs_ipc_data *apcs_data;
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struct regmap *regmap;
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struct resource *res;
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void __iomem *base;
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unsigned long i;
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int ret;
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apcs = devm_kzalloc(&pdev->dev, sizeof(*apcs), GFP_KERNEL);
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if (!apcs)
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return -ENOMEM;
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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base = devm_ioremap_resource(&pdev->dev, res);
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if (IS_ERR(base))
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return PTR_ERR(base);
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regmap = devm_regmap_init_mmio(&pdev->dev, base, &apcs_regmap_config);
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if (IS_ERR(regmap))
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return PTR_ERR(regmap);
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apcs_data = of_device_get_match_data(&pdev->dev);
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apcs->regmap = regmap;
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apcs->offset = apcs_data->offset;
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/* Initialize channel identifiers */
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for (i = 0; i < ARRAY_SIZE(apcs->mbox_chans); i++)
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apcs->mbox_chans[i].con_priv = (void *)i;
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apcs->mbox.dev = &pdev->dev;
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apcs->mbox.ops = &qcom_apcs_ipc_ops;
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apcs->mbox.chans = apcs->mbox_chans;
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apcs->mbox.num_chans = ARRAY_SIZE(apcs->mbox_chans);
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ret = devm_mbox_controller_register(&pdev->dev, &apcs->mbox);
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if (ret) {
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dev_err(&pdev->dev, "failed to register APCS IPC controller\n");
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return ret;
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}
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if (apcs_data->clk_name) {
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apcs->clk = platform_device_register_data(&pdev->dev,
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apcs_data->clk_name,
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PLATFORM_DEVID_NONE,
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NULL, 0);
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if (IS_ERR(apcs->clk))
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dev_err(&pdev->dev, "failed to register APCS clk\n");
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}
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platform_set_drvdata(pdev, apcs);
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return 0;
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}
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static int qcom_apcs_ipc_remove(struct platform_device *pdev)
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{
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struct qcom_apcs_ipc *apcs = platform_get_drvdata(pdev);
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struct platform_device *clk = apcs->clk;
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platform_device_unregister(clk);
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return 0;
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}
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/* .data is the offset of the ipc register within the global block */
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static const struct of_device_id qcom_apcs_ipc_of_match[] = {
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{ .compatible = "qcom,ipq6018-apcs-apps-global", .data = &ipq6018_apcs_data },
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{ .compatible = "qcom,ipq8074-apcs-apps-global", .data = &ipq8074_apcs_data },
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{ .compatible = "qcom,msm8916-apcs-kpss-global", .data = &msm8916_apcs_data },
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{ .compatible = "qcom,msm8994-apcs-kpss-global", .data = &msm8994_apcs_data },
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{ .compatible = "qcom,msm8996-apcs-hmss-global", .data = &msm8996_apcs_data },
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{ .compatible = "qcom,msm8998-apcs-hmss-global", .data = &msm8998_apcs_data },
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{ .compatible = "qcom,qcs404-apcs-apps-global", .data = &msm8916_apcs_data },
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{ .compatible = "qcom,sc7180-apss-shared", .data = &apps_shared_apcs_data },
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{ .compatible = "qcom,sc8180x-apss-shared", .data = &apps_shared_apcs_data },
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{ .compatible = "qcom,sdm660-apcs-hmss-global", .data = &sdm660_apcs_data },
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{ .compatible = "qcom,sdm845-apss-shared", .data = &apps_shared_apcs_data },
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{ .compatible = "qcom,sm8150-apss-shared", .data = &apps_shared_apcs_data },
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{ .compatible = "qcom,sdx55-apcs-gcc", .data = &sdx55_apcs_data },
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{}
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};
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MODULE_DEVICE_TABLE(of, qcom_apcs_ipc_of_match);
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static struct platform_driver qcom_apcs_ipc_driver = {
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.probe = qcom_apcs_ipc_probe,
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.remove = qcom_apcs_ipc_remove,
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.driver = {
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.name = "qcom_apcs_ipc",
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.of_match_table = qcom_apcs_ipc_of_match,
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},
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};
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static int __init qcom_apcs_ipc_init(void)
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{
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return platform_driver_register(&qcom_apcs_ipc_driver);
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}
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postcore_initcall(qcom_apcs_ipc_init);
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static void __exit qcom_apcs_ipc_exit(void)
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{
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platform_driver_unregister(&qcom_apcs_ipc_driver);
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}
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module_exit(qcom_apcs_ipc_exit);
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MODULE_LICENSE("GPL v2");
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MODULE_DESCRIPTION("Qualcomm APCS IPC driver");
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