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![Lee Jones](/assets/img/avatar_default.png)
It's odd for the return value to be assigned to a variable so many times, but never actually checked, but this has been the case since the driver's inception in 2012. If it hasn't caused any issues by now, it's probably unlikely to. Let's take it out, at least until someone finds a reason to start using it. Fixes the following W=1 kernel build warning: drivers/misc/lattice-ecp3-config.c: In function ‘firmware_load’: drivers/misc/lattice-ecp3-config.c:70:6: warning: variable ‘ret’ set but not used [-Wunused-but-set-variable] 70 | int ret; | ^~~ Cc: Stefan Roese <sr@denx.de> Signed-off-by: Lee Jones <lee.jones@linaro.org> Link: https://lore.kernel.org/r/20200701085853.164358-13-lee.jones@linaro.org Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
244 lines
5.6 KiB
C
244 lines
5.6 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* Copyright (C) 2012 Stefan Roese <sr@denx.de>
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*/
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#include <linux/device.h>
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#include <linux/firmware.h>
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#include <linux/module.h>
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#include <linux/errno.h>
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#include <linux/kernel.h>
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#include <linux/spi/spi.h>
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#include <linux/platform_device.h>
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#include <linux/delay.h>
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#include <asm/unaligned.h>
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#define FIRMWARE_NAME "lattice-ecp3.bit"
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/*
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* The JTAG ID's of the supported FPGA's. The ID is 32bit wide
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* reversed as noted in the manual.
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*/
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#define ID_ECP3_17 0xc2088080
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#define ID_ECP3_35 0xc2048080
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/* FPGA commands */
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#define FPGA_CMD_READ_ID 0x07 /* plus 24 bits */
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#define FPGA_CMD_READ_STATUS 0x09 /* plus 24 bits */
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#define FPGA_CMD_CLEAR 0x70
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#define FPGA_CMD_REFRESH 0x71
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#define FPGA_CMD_WRITE_EN 0x4a /* plus 2 bits */
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#define FPGA_CMD_WRITE_DIS 0x4f /* plus 8 bits */
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#define FPGA_CMD_WRITE_INC 0x41 /* plus 0 bits */
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/*
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* The status register is 32bit revered, DONE is bit 17 from the TN1222.pdf
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* (LatticeECP3 Slave SPI Port User's Guide)
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*/
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#define FPGA_STATUS_DONE 0x00004000
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#define FPGA_STATUS_CLEARED 0x00010000
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#define FPGA_CLEAR_TIMEOUT 5000 /* max. 5000ms for FPGA clear */
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#define FPGA_CLEAR_MSLEEP 10
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#define FPGA_CLEAR_LOOP_COUNT (FPGA_CLEAR_TIMEOUT / FPGA_CLEAR_MSLEEP)
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struct fpga_data {
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struct completion fw_loaded;
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};
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struct ecp3_dev {
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u32 jedec_id;
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char *name;
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};
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static const struct ecp3_dev ecp3_dev[] = {
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{
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.jedec_id = ID_ECP3_17,
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.name = "Lattice ECP3-17",
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},
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{
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.jedec_id = ID_ECP3_35,
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.name = "Lattice ECP3-35",
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},
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};
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static void firmware_load(const struct firmware *fw, void *context)
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{
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struct spi_device *spi = (struct spi_device *)context;
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struct fpga_data *data = spi_get_drvdata(spi);
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u8 *buffer;
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u8 txbuf[8];
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u8 rxbuf[8];
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int rx_len = 8;
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int i;
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u32 jedec_id;
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u32 status;
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if (fw == NULL) {
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dev_err(&spi->dev, "Cannot load firmware, aborting\n");
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return;
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}
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if (fw->size == 0) {
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dev_err(&spi->dev, "Error: Firmware size is 0!\n");
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return;
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}
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/* Fill dummy data (24 stuffing bits for commands) */
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txbuf[1] = 0x00;
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txbuf[2] = 0x00;
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txbuf[3] = 0x00;
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/* Trying to speak with the FPGA via SPI... */
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txbuf[0] = FPGA_CMD_READ_ID;
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spi_write_then_read(spi, txbuf, 8, rxbuf, rx_len);
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jedec_id = get_unaligned_be32(&rxbuf[4]);
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dev_dbg(&spi->dev, "FPGA JTAG ID=%08x\n", jedec_id);
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for (i = 0; i < ARRAY_SIZE(ecp3_dev); i++) {
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if (jedec_id == ecp3_dev[i].jedec_id)
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break;
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}
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if (i == ARRAY_SIZE(ecp3_dev)) {
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dev_err(&spi->dev,
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"Error: No supported FPGA detected (JEDEC_ID=%08x)!\n",
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jedec_id);
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return;
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}
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dev_info(&spi->dev, "FPGA %s detected\n", ecp3_dev[i].name);
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txbuf[0] = FPGA_CMD_READ_STATUS;
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spi_write_then_read(spi, txbuf, 8, rxbuf, rx_len);
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status = get_unaligned_be32(&rxbuf[4]);
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dev_dbg(&spi->dev, "FPGA Status=%08x\n", status);
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buffer = kzalloc(fw->size + 8, GFP_KERNEL);
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if (!buffer) {
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dev_err(&spi->dev, "Error: Can't allocate memory!\n");
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return;
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}
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/*
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* Insert WRITE_INC command into stream (one SPI frame)
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*/
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buffer[0] = FPGA_CMD_WRITE_INC;
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buffer[1] = 0xff;
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buffer[2] = 0xff;
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buffer[3] = 0xff;
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memcpy(buffer + 4, fw->data, fw->size);
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txbuf[0] = FPGA_CMD_REFRESH;
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spi_write(spi, txbuf, 4);
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txbuf[0] = FPGA_CMD_WRITE_EN;
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spi_write(spi, txbuf, 4);
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txbuf[0] = FPGA_CMD_CLEAR;
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spi_write(spi, txbuf, 4);
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/*
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* Wait for FPGA memory to become cleared
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*/
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for (i = 0; i < FPGA_CLEAR_LOOP_COUNT; i++) {
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txbuf[0] = FPGA_CMD_READ_STATUS;
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spi_write_then_read(spi, txbuf, 8, rxbuf, rx_len);
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status = get_unaligned_be32(&rxbuf[4]);
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if (status == FPGA_STATUS_CLEARED)
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break;
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msleep(FPGA_CLEAR_MSLEEP);
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}
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if (i == FPGA_CLEAR_LOOP_COUNT) {
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dev_err(&spi->dev,
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"Error: Timeout waiting for FPGA to clear (status=%08x)!\n",
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status);
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kfree(buffer);
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return;
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}
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dev_info(&spi->dev, "Configuring the FPGA...\n");
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spi_write(spi, buffer, fw->size + 8);
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txbuf[0] = FPGA_CMD_WRITE_DIS;
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spi_write(spi, txbuf, 4);
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txbuf[0] = FPGA_CMD_READ_STATUS;
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spi_write_then_read(spi, txbuf, 8, rxbuf, rx_len);
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status = get_unaligned_be32(&rxbuf[4]);
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dev_dbg(&spi->dev, "FPGA Status=%08x\n", status);
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/* Check result */
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if (status & FPGA_STATUS_DONE)
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dev_info(&spi->dev, "FPGA successfully configured!\n");
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else
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dev_info(&spi->dev, "FPGA not configured (DONE not set)\n");
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/*
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* Don't forget to release the firmware again
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*/
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release_firmware(fw);
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kfree(buffer);
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complete(&data->fw_loaded);
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}
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static int lattice_ecp3_probe(struct spi_device *spi)
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{
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struct fpga_data *data;
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int err;
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data = devm_kzalloc(&spi->dev, sizeof(*data), GFP_KERNEL);
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if (!data) {
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dev_err(&spi->dev, "Memory allocation for fpga_data failed\n");
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return -ENOMEM;
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}
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spi_set_drvdata(spi, data);
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init_completion(&data->fw_loaded);
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err = request_firmware_nowait(THIS_MODULE, FW_ACTION_HOTPLUG,
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FIRMWARE_NAME, &spi->dev,
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GFP_KERNEL, spi, firmware_load);
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if (err) {
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dev_err(&spi->dev, "Firmware loading failed with %d!\n", err);
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return err;
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}
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dev_info(&spi->dev, "FPGA bitstream configuration driver registered\n");
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return 0;
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}
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static int lattice_ecp3_remove(struct spi_device *spi)
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{
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struct fpga_data *data = spi_get_drvdata(spi);
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wait_for_completion(&data->fw_loaded);
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return 0;
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}
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static const struct spi_device_id lattice_ecp3_id[] = {
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{ "ecp3-17", 0 },
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{ "ecp3-35", 0 },
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{ }
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};
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MODULE_DEVICE_TABLE(spi, lattice_ecp3_id);
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static struct spi_driver lattice_ecp3_driver = {
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.driver = {
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.name = "lattice-ecp3",
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},
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.probe = lattice_ecp3_probe,
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.remove = lattice_ecp3_remove,
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.id_table = lattice_ecp3_id,
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};
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module_spi_driver(lattice_ecp3_driver);
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MODULE_AUTHOR("Stefan Roese <sr@denx.de>");
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MODULE_DESCRIPTION("Lattice ECP3 FPGA configuration via SPI");
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MODULE_LICENSE("GPL");
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MODULE_FIRMWARE(FIRMWARE_NAME);
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