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e8510d43f2
The OcteonTX (TX1/ThunderX) SPI controller does not support full duplex transactions. Set the appropriate flag such that the spi core will return -EINVAL on such transactions requested by chip drivers. This is an RFC as I need someone from Marvell/Cavium to confirm if this driver is used for other silicon that does support full duplex transfers (in which case we will need to identify that we are running on the ThunderX arch before setting the flag). Signed-off-by: Tim Harvey <tharvey@gateworks.com> Cc: Robert Richter <rrichter@marvell.com> Link: https://lore.kernel.org/r/1590680799-5640-1-git-send-email-tharvey@gateworks.com Signed-off-by: Mark Brown <broonie@kernel.org>
124 lines
2.7 KiB
C
124 lines
2.7 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Cavium ThunderX SPI driver.
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*
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* Copyright (C) 2016 Cavium Inc.
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* Authors: Jan Glauber <jglauber@cavium.com>
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*/
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#include <linux/module.h>
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#include <linux/pci.h>
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#include <linux/spi/spi.h>
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#include "spi-cavium.h"
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#define DRV_NAME "spi-thunderx"
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#define SYS_FREQ_DEFAULT 700000000 /* 700 Mhz */
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static int thunderx_spi_probe(struct pci_dev *pdev,
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const struct pci_device_id *ent)
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{
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struct device *dev = &pdev->dev;
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struct spi_master *master;
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struct octeon_spi *p;
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int ret;
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master = spi_alloc_master(dev, sizeof(struct octeon_spi));
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if (!master)
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return -ENOMEM;
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p = spi_master_get_devdata(master);
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ret = pcim_enable_device(pdev);
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if (ret)
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goto error;
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ret = pci_request_regions(pdev, DRV_NAME);
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if (ret)
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goto error;
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p->register_base = pcim_iomap(pdev, 0, pci_resource_len(pdev, 0));
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if (!p->register_base) {
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ret = -EINVAL;
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goto error;
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}
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p->regs.config = 0x1000;
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p->regs.status = 0x1008;
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p->regs.tx = 0x1010;
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p->regs.data = 0x1080;
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p->clk = devm_clk_get(dev, NULL);
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if (IS_ERR(p->clk)) {
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ret = PTR_ERR(p->clk);
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goto error;
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}
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ret = clk_prepare_enable(p->clk);
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if (ret)
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goto error;
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p->sys_freq = clk_get_rate(p->clk);
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if (!p->sys_freq)
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p->sys_freq = SYS_FREQ_DEFAULT;
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dev_info(dev, "Set system clock to %u\n", p->sys_freq);
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master->flags = SPI_MASTER_HALF_DUPLEX;
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master->num_chipselect = 4;
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master->mode_bits = SPI_CPHA | SPI_CPOL | SPI_CS_HIGH |
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SPI_LSB_FIRST | SPI_3WIRE;
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master->transfer_one_message = octeon_spi_transfer_one_message;
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master->bits_per_word_mask = SPI_BPW_MASK(8);
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master->max_speed_hz = OCTEON_SPI_MAX_CLOCK_HZ;
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master->dev.of_node = pdev->dev.of_node;
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pci_set_drvdata(pdev, master);
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ret = devm_spi_register_master(dev, master);
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if (ret)
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goto error;
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return 0;
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error:
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clk_disable_unprepare(p->clk);
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pci_release_regions(pdev);
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spi_master_put(master);
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return ret;
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}
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static void thunderx_spi_remove(struct pci_dev *pdev)
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{
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struct spi_master *master = pci_get_drvdata(pdev);
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struct octeon_spi *p;
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p = spi_master_get_devdata(master);
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if (!p)
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return;
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clk_disable_unprepare(p->clk);
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pci_release_regions(pdev);
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/* Put everything in a known state. */
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writeq(0, p->register_base + OCTEON_SPI_CFG(p));
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}
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static const struct pci_device_id thunderx_spi_pci_id_table[] = {
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{ PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, 0xa00b) },
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{ 0, }
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};
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MODULE_DEVICE_TABLE(pci, thunderx_spi_pci_id_table);
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static struct pci_driver thunderx_spi_driver = {
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.name = DRV_NAME,
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.id_table = thunderx_spi_pci_id_table,
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.probe = thunderx_spi_probe,
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.remove = thunderx_spi_remove,
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};
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module_pci_driver(thunderx_spi_driver);
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MODULE_DESCRIPTION("Cavium, Inc. ThunderX SPI bus driver");
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MODULE_AUTHOR("Jan Glauber");
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MODULE_LICENSE("GPL");
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