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And the nand_x_clk and nand_ecc_clk. Make the nand_x_clk be the main clock that is feeding the NAND IP and correct it's parent to be the l4_mp_clk. Signed-off-by: Dinh Nguyen <dinguyen@kernel.org> Link: https://lore.kernel.org/r/20200616202417.14376-2-dinguyen@kernel.org Signed-off-by: Stephen Boyd <sboyd@kernel.org> |
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.. | ||
clk-agilex.c | ||
clk-gate-a10.c | ||
clk-gate-s10.c | ||
clk-gate.c | ||
clk-periph-a10.c | ||
clk-periph-s10.c | ||
clk-periph.c | ||
clk-pll-a10.c | ||
clk-pll-s10.c | ||
clk-pll.c | ||
clk-s10.c | ||
clk.c | ||
clk.h | ||
Makefile | ||
stratix10-clk.h |