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Now that all architectures provide arch_atomic_long_*(), we can implement the generic bitops atop these rather than atop atomic_long_*(), and provide arch_*() forms of the bitops that are safe to use in noinstr code. Now that all architectures provide arch_atomic_long_*(), we can build the generic arch_*() bitops atop these, which can be safely used in noinstr code. The regular bitop wrappers are built atop these. As the generic non-atomic bitops use plain accesses, these will be implicitly instrumented unless they are inlined into noinstr functions (which is similar to arch_atomic*_read() when based on READ_ONCE()). The wrappers are modified so that where the underlying arch_*() function uses a plain access, no explicit instrumentation is added, as this is redundant and could result in confusing reports. Since function prototypes get excessively long with both an `arch_` prefix and `__always_inline` attribute, the return type and function attributes have been split onto a separate line, matching the style of the generated atomic headers. Signed-off-by: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Link: https://lore.kernel.org/r/20210713105253.7615-6-mark.rutland@arm.com
94 lines
2.6 KiB
C
94 lines
2.6 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef _ASM_GENERIC_BITOPS_LOCK_H_
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#define _ASM_GENERIC_BITOPS_LOCK_H_
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#include <linux/atomic.h>
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#include <linux/compiler.h>
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#include <asm/barrier.h>
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/**
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* arch_test_and_set_bit_lock - Set a bit and return its old value, for lock
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* @nr: Bit to set
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* @addr: Address to count from
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*
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* This operation is atomic and provides acquire barrier semantics if
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* the returned value is 0.
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* It can be used to implement bit locks.
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*/
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static __always_inline int
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arch_test_and_set_bit_lock(unsigned int nr, volatile unsigned long *p)
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{
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long old;
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unsigned long mask = BIT_MASK(nr);
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p += BIT_WORD(nr);
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if (READ_ONCE(*p) & mask)
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return 1;
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old = arch_atomic_long_fetch_or_acquire(mask, (atomic_long_t *)p);
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return !!(old & mask);
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}
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/**
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* arch_clear_bit_unlock - Clear a bit in memory, for unlock
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* @nr: the bit to set
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* @addr: the address to start counting from
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*
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* This operation is atomic and provides release barrier semantics.
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*/
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static __always_inline void
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arch_clear_bit_unlock(unsigned int nr, volatile unsigned long *p)
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{
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p += BIT_WORD(nr);
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arch_atomic_long_fetch_andnot_release(BIT_MASK(nr), (atomic_long_t *)p);
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}
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/**
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* arch___clear_bit_unlock - Clear a bit in memory, for unlock
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* @nr: the bit to set
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* @addr: the address to start counting from
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*
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* A weaker form of clear_bit_unlock() as used by __bit_lock_unlock(). If all
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* the bits in the word are protected by this lock some archs can use weaker
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* ops to safely unlock.
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*
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* See for example x86's implementation.
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*/
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static inline void
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arch___clear_bit_unlock(unsigned int nr, volatile unsigned long *p)
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{
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unsigned long old;
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p += BIT_WORD(nr);
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old = READ_ONCE(*p);
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old &= ~BIT_MASK(nr);
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arch_atomic_long_set_release((atomic_long_t *)p, old);
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}
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/**
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* arch_clear_bit_unlock_is_negative_byte - Clear a bit in memory and test if bottom
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* byte is negative, for unlock.
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* @nr: the bit to clear
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* @addr: the address to start counting from
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*
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* This is a bit of a one-trick-pony for the filemap code, which clears
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* PG_locked and tests PG_waiters,
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*/
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#ifndef arch_clear_bit_unlock_is_negative_byte
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static inline bool arch_clear_bit_unlock_is_negative_byte(unsigned int nr,
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volatile unsigned long *p)
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{
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long old;
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unsigned long mask = BIT_MASK(nr);
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p += BIT_WORD(nr);
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old = arch_atomic_long_fetch_andnot_release(mask, (atomic_long_t *)p);
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return !!(old & BIT(7));
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}
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#define arch_clear_bit_unlock_is_negative_byte arch_clear_bit_unlock_is_negative_byte
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#endif
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#include <asm-generic/bitops/instrumented-lock.h>
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#endif /* _ASM_GENERIC_BITOPS_LOCK_H_ */
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