220 lines
5.4 KiB
YAML
220 lines
5.4 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/pci/fsl,imx6q-pcie.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Freescale i.MX6 PCIe host controller
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maintainers:
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- Lucas Stach <l.stach@pengutronix.de>
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- Richard Zhu <hongxing.zhu@nxp.com>
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description: |+
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This PCIe host controller is based on the Synopsys DesignWare PCIe IP
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and thus inherits all the common properties defined in snps,dw-pcie.yaml.
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The controller instances are dual mode where in they can work either in
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Root Port mode or Endpoint mode but one at a time.
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See fsl,imx6q-pcie-ep.yaml for details on the Endpoint mode device tree
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bindings.
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properties:
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compatible:
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enum:
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- fsl,imx6q-pcie
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- fsl,imx6sx-pcie
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- fsl,imx6qp-pcie
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- fsl,imx7d-pcie
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- fsl,imx8mq-pcie
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- fsl,imx8mm-pcie
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- fsl,imx8mp-pcie
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- fsl,imx95-pcie
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clocks:
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minItems: 3
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items:
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- description: PCIe bridge clock.
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- description: PCIe bus clock.
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- description: PCIe PHY clock.
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- description: Additional required clock entry for imx6sx-pcie,
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imx6sx-pcie-ep, imx8mq-pcie, imx8mq-pcie-ep.
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clock-names:
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minItems: 3
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maxItems: 4
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interrupts:
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items:
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- description: builtin MSI controller.
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interrupt-names:
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items:
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- const: msi
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reset-gpio:
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description: Should specify the GPIO for controlling the PCI bus device
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reset signal. It's not polarity aware and defaults to active-low reset
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sequence (L=reset state, H=operation state) (optional required).
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reset-gpio-active-high:
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description: If present then the reset sequence using the GPIO
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specified in the "reset-gpio" property is reversed (H=reset state,
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L=operation state) (optional required).
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type: boolean
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required:
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- compatible
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- reg
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- reg-names
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- "#address-cells"
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- "#size-cells"
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- device_type
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- bus-range
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- ranges
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- interrupts
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- interrupt-names
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- "#interrupt-cells"
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- interrupt-map-mask
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- interrupt-map
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allOf:
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- $ref: /schemas/pci/snps,dw-pcie.yaml#
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- $ref: /schemas/pci/fsl,imx6q-pcie-common.yaml#
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- if:
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properties:
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compatible:
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enum:
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- fsl,imx6q-pcie
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- fsl,imx6sx-pcie
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- fsl,imx6qp-pcie
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- fsl,imx7d-pcie
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- fsl,imx8mq-pcie
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- fsl,imx8mm-pcie
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- fsl,imx8mp-pcie
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then:
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properties:
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reg:
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maxItems: 2
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reg-names:
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items:
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- const: dbi
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- const: config
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- if:
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properties:
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compatible:
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enum:
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- fsl,imx95-pcie
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then:
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properties:
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reg:
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minItems: 4
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maxItems: 4
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reg-names:
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items:
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- const: dbi
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- const: config
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- const: atu
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- const: app
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- if:
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properties:
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compatible:
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enum:
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- fsl,imx6sx-pcie
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then:
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properties:
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clocks:
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minItems: 4
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clock-names:
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items:
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- const: pcie
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- const: pcie_bus
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- const: pcie_phy
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- const: pcie_inbound_axi
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- if:
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properties:
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compatible:
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enum:
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- fsl,imx8mq-pcie
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- fsl,imx95-pcie
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then:
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properties:
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clocks:
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minItems: 4
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clock-names:
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items:
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- const: pcie
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- const: pcie_bus
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- const: pcie_phy
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- const: pcie_aux
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- if:
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properties:
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compatible:
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enum:
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- fsl,imx6q-pcie
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- fsl,imx6qp-pcie
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- fsl,imx7d-pcie
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then:
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properties:
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clocks:
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maxItems: 3
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clock-names:
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items:
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- const: pcie
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- const: pcie_bus
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- const: pcie_phy
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- if:
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properties:
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compatible:
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enum:
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- fsl,imx8mm-pcie
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- fsl,imx8mp-pcie
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then:
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properties:
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clocks:
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maxItems: 3
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clock-names:
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items:
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- const: pcie
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- const: pcie_bus
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- const: pcie_aux
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/clock/imx6qdl-clock.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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pcie: pcie@1ffc000 {
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compatible = "fsl,imx6q-pcie";
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reg = <0x01ffc000 0x04000>,
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<0x01f00000 0x80000>;
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reg-names = "dbi", "config";
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#address-cells = <3>;
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#size-cells = <2>;
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device_type = "pci";
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bus-range = <0x00 0xff>;
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ranges = <0x81000000 0 0 0x01f80000 0 0x00010000>,
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<0x82000000 0 0x01000000 0x01000000 0 0x00f00000>;
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num-lanes = <1>;
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interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "msi";
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 0x7>;
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interrupt-map = <0 0 0 1 &gpc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 0 2 &gpc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 0 3 &gpc GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 0 4 &gpc GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clks IMX6QDL_CLK_PCIE_AXI>,
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<&clks IMX6QDL_CLK_LVDS1_GATE>,
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<&clks IMX6QDL_CLK_PCIE_REF_125M>;
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clock-names = "pcie", "pcie_bus", "pcie_phy";
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};
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...
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