167 lines
5.0 KiB
YAML
167 lines
5.0 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/pci/qcom,pcie-sa8775p.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm SA8775p PCI Express Root Complex
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maintainers:
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- Bjorn Andersson <andersson@kernel.org>
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- Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
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description:
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Qualcomm SA8775p SoC PCIe root complex controller is based on the Synopsys
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DesignWare PCIe IP.
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properties:
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compatible:
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const: qcom,pcie-sa8775p
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reg:
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minItems: 6
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maxItems: 6
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reg-names:
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items:
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- const: parf # Qualcomm specific registers
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- const: dbi # DesignWare PCIe registers
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- const: elbi # External local bus interface registers
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- const: atu # ATU address space
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- const: config # PCIe configuration space
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- const: mhi # MHI registers
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clocks:
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minItems: 5
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maxItems: 5
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clock-names:
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items:
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- const: aux # Auxiliary clock
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- const: cfg # Configuration clock
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- const: bus_master # Master AXI clock
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- const: bus_slave # Slave AXI clock
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- const: slave_q2a # Slave Q2A clock
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interrupts:
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minItems: 8
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maxItems: 8
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interrupt-names:
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items:
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- const: msi0
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- const: msi1
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- const: msi2
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- const: msi3
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- const: msi4
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- const: msi5
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- const: msi6
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- const: msi7
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resets:
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maxItems: 1
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reset-names:
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items:
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- const: pci
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required:
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- interconnects
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- interconnect-names
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allOf:
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- $ref: qcom,pcie-common.yaml#
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/clock/qcom,sa8775p-gcc.h>
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#include <dt-bindings/clock/qcom,rpmh.h>
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/interconnect/qcom,sa8775p-rpmh.h>
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soc {
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#address-cells = <2>;
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#size-cells = <2>;
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pcie@1c00000 {
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compatible = "qcom,pcie-sa8775p";
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reg = <0x0 0x01c00000 0x0 0x3000>,
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<0x0 0x40000000 0x0 0xf20>,
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<0x0 0x40000f20 0x0 0xa8>,
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<0x0 0x40001000 0x0 0x4000>,
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<0x0 0x40100000 0x0 0x100000>,
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<0x0 0x01c03000 0x0 0x1000>;
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reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi";
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ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>,
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<0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>;
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bus-range = <0x00 0xff>;
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device_type = "pci";
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linux,pci-domain = <0>;
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num-lanes = <2>;
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#address-cells = <3>;
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#size-cells = <2>;
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assigned-clocks = <&gcc GCC_PCIE_0_AUX_CLK>;
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assigned-clock-rates = <19200000>;
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clocks = <&gcc GCC_PCIE_0_AUX_CLK>,
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<&gcc GCC_PCIE_0_CFG_AHB_CLK>,
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<&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
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<&gcc GCC_PCIE_0_SLV_AXI_CLK>,
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<&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>;
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clock-names = "aux",
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"cfg",
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"bus_master",
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"bus_slave",
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"slave_q2a";
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dma-coherent;
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interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "msi0",
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"msi1",
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"msi2",
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"msi3",
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"msi4",
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"msi5",
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"msi6",
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"msi7";
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 0x7>;
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interrupt-map = <0 0 0 1 &intc GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 0 2 &intc GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 0 3 &intc GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 0 4 &intc GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH>;
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interconnects = <&pcie_anoc MASTER_PCIE_0 0 &mc_virt SLAVE_EBI1 0>,
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<&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_0 0>;
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interconnect-names = "pcie-mem", "cpu-pcie";
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iommu-map = <0x0 &pcie_smmu 0x0000 0x1>,
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<0x100 &pcie_smmu 0x0001 0x1>;
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phys = <&pcie0_phy>;
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phy-names = "pciephy";
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power-domains = <&gcc PCIE_0_GDSC>;
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resets = <&gcc GCC_PCIE_0_BCR>;
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reset-names = "pci";
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perst-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>;
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wake-gpios = <&tlmm 0 GPIO_ACTIVE_HIGH>;
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};
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};
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