167 lines
4.9 KiB
YAML
167 lines
4.9 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/pci/qcom,pcie-sc7280.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm SC7280 PCI Express Root Complex
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maintainers:
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- Bjorn Andersson <andersson@kernel.org>
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- Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
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description:
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Qualcomm SC7280 SoC PCIe root complex controller is based on the Synopsys
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DesignWare PCIe IP.
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properties:
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compatible:
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const: qcom,pcie-sc7280
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reg:
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minItems: 5
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maxItems: 6
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reg-names:
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minItems: 5
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items:
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- const: parf # Qualcomm specific registers
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- const: dbi # DesignWare PCIe registers
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- const: elbi # External local bus interface registers
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- const: atu # ATU address space
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- const: config # PCIe configuration space
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- const: mhi # MHI registers
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clocks:
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minItems: 13
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maxItems: 13
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clock-names:
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items:
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- const: pipe # PIPE clock
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- const: pipe_mux # PIPE MUX
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- const: phy_pipe # PIPE output clock
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- const: ref # REFERENCE clock
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- const: aux # Auxiliary clock
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- const: cfg # Configuration clock
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- const: bus_master # Master AXI clock
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- const: bus_slave # Slave AXI clock
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- const: slave_q2a # Slave Q2A clock
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- const: tbu # PCIe TBU clock
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- const: ddrss_sf_tbu # PCIe SF TBU clock
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- const: aggre0 # Aggre NoC PCIe CENTER SF AXI clock
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- const: aggre1 # Aggre NoC PCIe1 AXI clock
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interrupts:
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maxItems: 1
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interrupt-names:
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items:
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- const: msi
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resets:
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maxItems: 1
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reset-names:
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items:
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- const: pci
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vddpe-3v3-supply:
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description: PCIe endpoint power supply
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allOf:
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- $ref: qcom,pcie-common.yaml#
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/clock/qcom,gcc-sc7280.h>
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#include <dt-bindings/clock/qcom,rpmh.h>
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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soc {
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#address-cells = <2>;
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#size-cells = <2>;
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pcie@1c08000 {
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compatible = "qcom,pcie-sc7280";
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reg = <0 0x01c08000 0 0x3000>,
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<0 0x40000000 0 0xf1d>,
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<0 0x40000f20 0 0xa8>,
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<0 0x40001000 0 0x1000>,
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<0 0x40100000 0 0x100000>;
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reg-names = "parf", "dbi", "elbi", "atu", "config";
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ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>,
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<0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>;
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bus-range = <0x00 0xff>;
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device_type = "pci";
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linux,pci-domain = <1>;
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num-lanes = <2>;
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#address-cells = <3>;
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#size-cells = <2>;
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assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>;
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assigned-clock-rates = <19200000>;
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clocks = <&gcc GCC_PCIE_1_PIPE_CLK>,
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<&gcc GCC_PCIE_1_PIPE_CLK_SRC>,
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<&pcie1_phy>,
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<&rpmhcc RPMH_CXO_CLK>,
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<&gcc GCC_PCIE_1_AUX_CLK>,
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<&gcc GCC_PCIE_1_CFG_AHB_CLK>,
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<&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
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<&gcc GCC_PCIE_1_SLV_AXI_CLK>,
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<&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>,
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<&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>,
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<&gcc GCC_DDRSS_PCIE_SF_CLK>,
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<&gcc GCC_AGGRE_NOC_PCIE_CENTER_SF_AXI_CLK>,
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<&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>;
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clock-names = "pipe",
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"pipe_mux",
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"phy_pipe",
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"ref",
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"aux",
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"cfg",
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"bus_master",
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"bus_slave",
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"slave_q2a",
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"tbu",
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"ddrss_sf_tbu",
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"aggre0",
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"aggre1";
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dma-coherent;
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interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "msi";
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 0x7>;
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interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 0 2 &intc 0 0 0 435 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 0 3 &intc 0 0 0 438 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 0 4 &intc 0 0 0 439 IRQ_TYPE_LEVEL_HIGH>;
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iommu-map = <0x0 &apps_smmu 0x1c80 0x1>,
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<0x100 &apps_smmu 0x1c81 0x1>;
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phys = <&pcie1_phy>;
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phy-names = "pciephy";
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pinctrl-names = "default";
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pinctrl-0 = <&pcie1_clkreq_n>;
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power-domains = <&gcc GCC_PCIE_1_GDSC>;
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resets = <&gcc GCC_PCIE_1_BCR>;
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reset-names = "pci";
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perst-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>;
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vddpe-3v3-supply = <&pp3300_ssd>;
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};
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};
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