195 lines
7.2 KiB
YAML
195 lines
7.2 KiB
YAML
# SPDX-License-Identifier: GPL-2.0
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/pci/snps,dw-pcie-ep.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Synopsys DesignWare PCIe endpoint interface
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maintainers:
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- Jingoo Han <jingoohan1@gmail.com>
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- Gustavo Pimentel <gustavo.pimentel@synopsys.com>
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description: |
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Synopsys DesignWare PCIe host controller endpoint
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# Please create a separate DT-schema for your DWC PCIe Endpoint controller
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# and make sure it's assigned with the vendor-specific compatible string.
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select:
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properties:
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compatible:
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const: snps,dw-pcie-ep
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required:
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- compatible
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allOf:
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- $ref: /schemas/pci/pci-ep.yaml#
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- $ref: /schemas/pci/snps,dw-pcie-common.yaml#
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properties:
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reg:
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description:
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DBI, DBI2 reg-spaces and outbound memory window are required for the
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normal controller functioning. iATU memory IO region is also required
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if the space is unrolled (IP-core version >= 4.80a).
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minItems: 2
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maxItems: 7
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reg-names:
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minItems: 2
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maxItems: 7
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items:
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oneOf:
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- description:
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Basic DWC PCIe controller configuration-space accessible over
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the DBI interface. This memory space is either activated with
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CDM/ELBI = 0 and CS2 = 0 or is a contiguous memory region
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with all spaces. Note iATU/eDMA CSRs are indirectly accessible
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via the PL viewports on the DWC PCIe controllers older than
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v4.80a.
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const: dbi
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- description:
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Shadow DWC PCIe config-space registers. This space is selected
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by setting CDM/ELBI = 0 and CS2 = 1. This is an intermix of
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the PCI-SIG PCIe CFG-space with the shadow registers for some
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PCI Header space, PCI Standard and Extended Structures. It's
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mainly relevant for the end-point controller configuration,
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but still there are some shadow registers available for the
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Root Port mode too.
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const: dbi2
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- description:
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External Local Bus registers. It's an application-dependent
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registers normally defined by the platform engineers. The space
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can be selected by setting CDM/ELBI = 1 and CS2 = 0 wires or can
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be accessed over some platform-specific means (for instance
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as a part of a system controller).
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enum: [ elbi, app ]
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- description:
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iATU/eDMA registers common for all device functions. It's an
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unrolled memory space with the internal Address Translation
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Unit and Enhanced DMA, which is selected by setting CDM/ELBI = 1
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and CS2 = 1. For IP-core releases prior v4.80a, these registers
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have been programmed via an indirect addressing scheme using a
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set of viewport CSRs mapped into the PL space. Note iATU is
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normally mapped to the 0x0 address of this region, while eDMA
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is available at 0x80000 base address.
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const: atu
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- description:
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Platform-specific eDMA registers. Some platforms may have eDMA
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CSRs mapped in a non-standard base address. The registers offset
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can be changed or the MS/LS-bits of the address can be attached
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in an additional RTL block before the MEM-IO transactions reach
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the DW PCIe slave interface.
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const: dma
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- description:
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PHY/PCS configuration registers. Some platforms can have the
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PCS and PHY CSRs accessible over a dedicated memory mapped
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region, but mainly these registers are indirectly accessible
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either by means of the embedded PHY viewport schema or by some
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platform-specific method.
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const: phy
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- description:
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Outbound iATU-capable memory-region which will be used to
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generate various application-specific traffic on the PCIe bus
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hierarchy. It's usage scenario depends on the endpoint
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functionality, for instance it can be used to create MSI(X)
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messages.
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const: addr_space
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- description:
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Vendor-specific CSR names. Consider using the generic names above
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for new bindings.
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oneOf:
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- description: See native 'elbi/app' CSR region for details.
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enum: [ link, appl ]
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- description: See native 'atu' CSR region for details.
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enum: [ atu_dma ]
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allOf:
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- contains:
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const: dbi
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- contains:
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const: addr_space
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interrupts:
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description:
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There is no mandatory IRQ signals for the normal controller functioning,
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but in addition to the native set the platforms may have a link- or
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PM-related IRQs specified.
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minItems: 1
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maxItems: 20
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interrupt-names:
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minItems: 1
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maxItems: 20
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items:
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oneOf:
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- description:
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Controller request to read or write virtual product data
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from/to the VPD capability registers.
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const: vpd
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- description:
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Link Equalization Request flag is set in the Link Status 2
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register (applicable if the corresponding IRQ is enabled in
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the Link Control 3 register).
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const: l_eq
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- description:
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Indicates that the eDMA Tx/Rx transfer is complete or that an
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error has occurred on the corresponding channel. eDMA can have
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eight Tx (Write) and Rx (Read) eDMA channels thus supporting up
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to 16 IRQ signals all together. Write eDMA channels shall go
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first in the ordered row as per default edma_int[*] bus setup.
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pattern: '^dma([0-9]|1[0-5])?$'
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- description:
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PCIe protocol correctable error or a Data Path protection
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correctable error is detected by the automotive/safety
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feature.
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const: sft_ce
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- description:
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Indicates that the internal safety mechanism has detected an
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uncorrectable error.
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const: sft_ue
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- description:
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Application-specific IRQ raised depending on the vendor-specific
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events basis.
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const: app
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- description:
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Vendor-specific IRQ names. Consider using the generic names above
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for new bindings.
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oneOf:
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- description: See native "app" IRQ for details
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enum: [ intr ]
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max-functions:
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maximum: 32
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required:
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- compatible
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- reg
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- reg-names
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additionalProperties: true
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examples:
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- |
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pcie-ep@dfd00000 {
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compatible = "snps,dw-pcie-ep";
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reg = <0xdfc00000 0x0001000>, /* IP registers 1 */
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<0xdfc01000 0x0001000>, /* IP registers 2 */
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<0xd0000000 0x2000000>; /* Configuration space */
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reg-names = "dbi", "dbi2", "addr_space";
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interrupts = <23>, <24>;
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interrupt-names = "dma0", "dma1";
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clocks = <&sys_clk 12>, <&sys_clk 24>;
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clock-names = "dbi", "ref";
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resets = <&sys_rst 12>, <&sys_rst 24>;
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reset-names = "dbi", "phy";
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phys = <&pcie_phy0>, <&pcie_phy1>, <&pcie_phy2>, <&pcie_phy3>;
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phy-names = "pcie0", "pcie1", "pcie2", "pcie3";
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max-link-speed = <3>;
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max-functions = /bits/ 8 <4>;
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};
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