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120931db07
The UIP timeout is hardcoded to 10ms for all RTC reads, but in some
contexts this might not be enough time. Add a timeout parameter to
mc146818_get_time() and mc146818_get_time_callback().
If UIP timeout is configured by caller to be >=100 ms and a call
takes this long, log a warning.
Make all callers use 10ms to ensure no functional changes.
Cc: <stable@vger.kernel.org> # 6.1.y
Fixes: ec5895c0f2 ("rtc: mc146818-lib: extract mc146818_avoid_UIP")
Signed-off-by: Mario Limonciello <mario.limonciello@amd.com>
Tested-by: Mateusz Jończyk <mat.jonczyk@o2.pl>
Reviewed-by: Mateusz Jończyk <mat.jonczyk@o2.pl>
Acked-by: Mateusz Jończyk <mat.jonczyk@o2.pl>
Link: https://lore.kernel.org/r/20231128053653.101798-4-mario.limonciello@amd.com
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
136 lines
4.7 KiB
C
136 lines
4.7 KiB
C
/* mc146818rtc.h - register definitions for the Real-Time-Clock / CMOS RAM
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* Copyright Torsten Duwe <duwe@informatik.uni-erlangen.de> 1993
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* derived from Data Sheet, Copyright Motorola 1984 (!).
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* It was written to be part of the Linux operating system.
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*/
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/* permission is hereby granted to copy, modify and redistribute this code
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* in terms of the GNU Library General Public License, Version 2 or later,
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* at your option.
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*/
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#ifndef _MC146818RTC_H
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#define _MC146818RTC_H
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#include <asm/io.h>
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#include <linux/rtc.h> /* get the user-level API */
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#include <asm/mc146818rtc.h> /* register access macros */
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#include <linux/bcd.h>
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#include <linux/delay.h>
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#include <linux/pm-trace.h>
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#ifdef __KERNEL__
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#include <linux/spinlock.h> /* spinlock_t */
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extern spinlock_t rtc_lock; /* serialize CMOS RAM access */
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/* Some RTCs extend the mc146818 register set to support alarms of more
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* than 24 hours in the future; or dates that include a century code.
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* This platform_data structure can pass this information to the driver.
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*
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* Also, some platforms need suspend()/resume() hooks to kick in special
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* handling of wake alarms, e.g. activating ACPI BIOS hooks or setting up
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* a separate wakeup alarm used by some almost-clone chips.
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*/
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struct cmos_rtc_board_info {
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void (*wake_on)(struct device *dev);
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void (*wake_off)(struct device *dev);
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u32 flags;
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#define CMOS_RTC_FLAGS_NOFREQ (1 << 0)
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int address_space;
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u8 rtc_day_alarm; /* zero, or register index */
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u8 rtc_mon_alarm; /* zero, or register index */
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u8 rtc_century; /* zero, or register index */
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};
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#endif
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/**********************************************************************
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* register summary
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**********************************************************************/
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#define RTC_SECONDS 0
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#define RTC_SECONDS_ALARM 1
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#define RTC_MINUTES 2
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#define RTC_MINUTES_ALARM 3
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#define RTC_HOURS 4
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#define RTC_HOURS_ALARM 5
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/* RTC_*_alarm is always true if 2 MSBs are set */
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# define RTC_ALARM_DONT_CARE 0xC0
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#define RTC_DAY_OF_WEEK 6
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#define RTC_DAY_OF_MONTH 7
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#define RTC_MONTH 8
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#define RTC_YEAR 9
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/* control registers - Moto names
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*/
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#define RTC_REG_A 10
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#define RTC_REG_B 11
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#define RTC_REG_C 12
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#define RTC_REG_D 13
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/**********************************************************************
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* register details
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**********************************************************************/
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#define RTC_FREQ_SELECT RTC_REG_A
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/* update-in-progress - set to "1" 244 microsecs before RTC goes off the bus,
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* reset after update (may take 1.984ms @ 32768Hz RefClock) is complete,
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* totalling to a max high interval of 2.228 ms.
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*/
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# define RTC_UIP 0x80
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# define RTC_DIV_CTL 0x70
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/* divider control: refclock values 4.194 / 1.049 MHz / 32.768 kHz */
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# define RTC_REF_CLCK_4MHZ 0x00
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# define RTC_REF_CLCK_1MHZ 0x10
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# define RTC_REF_CLCK_32KHZ 0x20
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/* 2 values for divider stage reset, others for "testing purposes only" */
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# define RTC_DIV_RESET1 0x60
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# define RTC_DIV_RESET2 0x70
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/* In AMD BKDG bit 5 and 6 are reserved, bit 4 is for select dv0 bank */
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# define RTC_AMD_BANK_SELECT 0x10
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/* Periodic intr. / Square wave rate select. 0=none, 1=32.8kHz,... 15=2Hz */
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# define RTC_RATE_SELECT 0x0F
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/**********************************************************************/
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#define RTC_CONTROL RTC_REG_B
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# define RTC_SET 0x80 /* disable updates for clock setting */
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# define RTC_PIE 0x40 /* periodic interrupt enable */
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# define RTC_AIE 0x20 /* alarm interrupt enable */
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# define RTC_UIE 0x10 /* update-finished interrupt enable */
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# define RTC_SQWE 0x08 /* enable square-wave output */
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# define RTC_DM_BINARY 0x04 /* all time/date values are BCD if clear */
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# define RTC_24H 0x02 /* 24 hour mode - else hours bit 7 means pm */
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# define RTC_DST_EN 0x01 /* auto switch DST - works f. USA only */
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/**********************************************************************/
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#define RTC_INTR_FLAGS RTC_REG_C
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/* caution - cleared by read */
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# define RTC_IRQF 0x80 /* any of the following 3 is active */
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# define RTC_PF 0x40
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# define RTC_AF 0x20
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# define RTC_UF 0x10
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/**********************************************************************/
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#define RTC_VALID RTC_REG_D
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# define RTC_VRT 0x80 /* valid RAM and time */
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/**********************************************************************/
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#ifndef ARCH_RTC_LOCATION /* Override by <asm/mc146818rtc.h>? */
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#define RTC_IO_EXTENT 0x8
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#define RTC_IO_EXTENT_USED 0x2
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#define RTC_IOMAPPED 1 /* Default to I/O mapping. */
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#else
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#define RTC_IO_EXTENT_USED RTC_IO_EXTENT
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#endif /* ARCH_RTC_LOCATION */
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bool mc146818_does_rtc_work(void);
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int mc146818_get_time(struct rtc_time *time, int timeout);
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int mc146818_set_time(struct rtc_time *time);
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bool mc146818_avoid_UIP(void (*callback)(unsigned char seconds, void *param),
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int timeout,
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void *param);
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#endif /* _MC146818RTC_H */
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