Jiancheng Xue 707d33cb0b clk: hisilicon: add CRG driver for Hi3798CV200 SoC ... Add CRG driver for Hi3798CV200 SoC. CRG(Clock and Reset Generator) module generates clock and reset signals used by other module blocks on SoC. Signed-off-by: Jiancheng Xue <xuejiancheng@hisilicon.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>		2016-11-11 15:43:49 -08:00
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clk-hi3519.c	clk: hisilicon: hi3519: add driver remove path and fix some issues	2016-06-30 12:35:20 -07:00
clk-hi3620.c	clk: hisilicon: Remove CLK_IS_ROOT	2016-03-02 17:43:32 -08:00
clk-hi6220-stub.c	clk: hisilicon: Remove CLK_IS_ROOT	2016-03-02 17:43:32 -08:00
clk-hi6220.c	clk: hi6220: Change syspll and media_syspll clk to 1.19GHz	2016-07-06 15:20:31 -07:00
clk-hip04.c	clk: hisilicon: Remove CLK_IS_ROOT	2016-03-02 17:43:32 -08:00
clk-hix5hd2.c	clk: hisilicon: Remove CLK_IS_ROOT	2016-03-02 17:43:32 -08:00
clk.c	clk: hisilicon: add error processing for hisi_clk_register_* functions	2016-06-30 12:35:11 -07:00
clk.h	clk: hisilicon: add hisi_clk_unregister_* functions	2016-06-30 12:35:18 -07:00
clkdivider-hi6220.c	clk: hi6220: fix missing clk.h include	2016-06-20 17:45:13 -07:00
clkgate-separated.c	clk: hisilicon: Remove clk.h include	2015-07-20 10:53:06 -07:00
crg-hi3798cv200.c	clk: hisilicon: add CRG driver for Hi3798CV200 SoC	2016-11-11 15:43:49 -08:00
crg.h	clk: hisilicon: add CRG driver for Hi3798CV200 SoC	2016-11-11 15:43:49 -08:00
Kconfig	clk: hisilicon: add CRG driver for Hi3798CV200 SoC	2016-11-11 15:43:49 -08:00
Makefile	clk: hisilicon: add CRG driver for Hi3798CV200 SoC	2016-11-11 15:43:49 -08:00
reset.c	reset: hisilicon: change the definition of hisi_reset_init	2016-06-30 12:33:22 -07:00
reset.h	reset: hisilicon: change the definition of hisi_reset_init	2016-06-30 12:33:22 -07:00