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![Sudip Mukherjee](/assets/img/avatar_default.png)
If of_iomap() or any other subsequent function fails moxart_timer_init() exits without freeing memory and unmapping the timer base. Add proper cleanup points. Signed-off-by: Sudip Mukherjee <sudip.mukherjee@codethink.co.uk> Cc: Daniel Lezcano <daniel.lezcano@linaro.org> Cc: Sudip Mukherjee <sudipm.mukherjee@gmail.com> Link: http://lkml.kernel.org/r/1482099996-1524-1-git-send-email-sudipm.mukherjee@gmail.com Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
256 lines
6.6 KiB
C
256 lines
6.6 KiB
C
/*
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* MOXA ART SoCs timer handling.
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*
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* Copyright (C) 2013 Jonas Jensen
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*
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* Jonas Jensen <jonas.jensen@gmail.com>
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#include <linux/clk.h>
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#include <linux/clockchips.h>
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <linux/irqreturn.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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#include <linux/io.h>
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#include <linux/clocksource.h>
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#include <linux/bitops.h>
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#include <linux/slab.h>
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#define TIMER1_BASE 0x00
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#define TIMER2_BASE 0x10
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#define TIMER3_BASE 0x20
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#define REG_COUNT 0x0 /* writable */
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#define REG_LOAD 0x4
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#define REG_MATCH1 0x8
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#define REG_MATCH2 0xC
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#define TIMER_CR 0x30
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#define TIMER_INTR_STATE 0x34
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#define TIMER_INTR_MASK 0x38
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/*
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* Moxart TIMER_CR flags:
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*
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* MOXART_CR_*_CLOCK 0: PCLK, 1: EXT1CLK
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* MOXART_CR_*_INT overflow interrupt enable bit
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*/
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#define MOXART_CR_1_ENABLE BIT(0)
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#define MOXART_CR_1_CLOCK BIT(1)
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#define MOXART_CR_1_INT BIT(2)
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#define MOXART_CR_2_ENABLE BIT(3)
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#define MOXART_CR_2_CLOCK BIT(4)
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#define MOXART_CR_2_INT BIT(5)
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#define MOXART_CR_3_ENABLE BIT(6)
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#define MOXART_CR_3_CLOCK BIT(7)
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#define MOXART_CR_3_INT BIT(8)
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#define MOXART_CR_COUNT_UP BIT(9)
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#define MOXART_TIMER1_ENABLE (MOXART_CR_2_ENABLE | MOXART_CR_1_ENABLE)
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#define MOXART_TIMER1_DISABLE (MOXART_CR_2_ENABLE)
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/*
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* The ASpeed variant of the IP block has a different layout
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* for the control register
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*/
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#define ASPEED_CR_1_ENABLE BIT(0)
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#define ASPEED_CR_1_CLOCK BIT(1)
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#define ASPEED_CR_1_INT BIT(2)
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#define ASPEED_CR_2_ENABLE BIT(4)
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#define ASPEED_CR_2_CLOCK BIT(5)
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#define ASPEED_CR_2_INT BIT(6)
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#define ASPEED_CR_3_ENABLE BIT(8)
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#define ASPEED_CR_3_CLOCK BIT(9)
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#define ASPEED_CR_3_INT BIT(10)
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#define ASPEED_TIMER1_ENABLE (ASPEED_CR_2_ENABLE | ASPEED_CR_1_ENABLE)
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#define ASPEED_TIMER1_DISABLE (ASPEED_CR_2_ENABLE)
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struct moxart_timer {
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void __iomem *base;
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unsigned int t1_disable_val;
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unsigned int t1_enable_val;
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unsigned int count_per_tick;
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struct clock_event_device clkevt;
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};
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static inline struct moxart_timer *to_moxart(struct clock_event_device *evt)
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{
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return container_of(evt, struct moxart_timer, clkevt);
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}
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static inline void moxart_disable(struct clock_event_device *evt)
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{
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struct moxart_timer *timer = to_moxart(evt);
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writel(timer->t1_disable_val, timer->base + TIMER_CR);
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}
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static inline void moxart_enable(struct clock_event_device *evt)
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{
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struct moxart_timer *timer = to_moxart(evt);
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writel(timer->t1_enable_val, timer->base + TIMER_CR);
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}
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static int moxart_shutdown(struct clock_event_device *evt)
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{
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moxart_disable(evt);
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return 0;
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}
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static int moxart_set_oneshot(struct clock_event_device *evt)
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{
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moxart_disable(evt);
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writel(~0, to_moxart(evt)->base + TIMER1_BASE + REG_LOAD);
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return 0;
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}
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static int moxart_set_periodic(struct clock_event_device *evt)
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{
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struct moxart_timer *timer = to_moxart(evt);
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moxart_disable(evt);
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writel(timer->count_per_tick, timer->base + TIMER1_BASE + REG_LOAD);
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writel(0, timer->base + TIMER1_BASE + REG_MATCH1);
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moxart_enable(evt);
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return 0;
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}
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static int moxart_clkevt_next_event(unsigned long cycles,
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struct clock_event_device *evt)
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{
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struct moxart_timer *timer = to_moxart(evt);
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u32 u;
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moxart_disable(evt);
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u = readl(timer->base + TIMER1_BASE + REG_COUNT) - cycles;
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writel(u, timer->base + TIMER1_BASE + REG_MATCH1);
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moxart_enable(evt);
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return 0;
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}
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static irqreturn_t moxart_timer_interrupt(int irq, void *dev_id)
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{
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struct clock_event_device *evt = dev_id;
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evt->event_handler(evt);
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return IRQ_HANDLED;
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}
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static int __init moxart_timer_init(struct device_node *node)
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{
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int ret, irq;
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unsigned long pclk;
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struct clk *clk;
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struct moxart_timer *timer;
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timer = kzalloc(sizeof(*timer), GFP_KERNEL);
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if (!timer)
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return -ENOMEM;
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timer->base = of_iomap(node, 0);
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if (!timer->base) {
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pr_err("%s: of_iomap failed\n", node->full_name);
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ret = -ENXIO;
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goto out_free;
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}
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irq = irq_of_parse_and_map(node, 0);
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if (irq <= 0) {
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pr_err("%s: irq_of_parse_and_map failed\n", node->full_name);
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ret = -EINVAL;
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goto out_unmap;
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}
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clk = of_clk_get(node, 0);
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if (IS_ERR(clk)) {
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pr_err("%s: of_clk_get failed\n", node->full_name);
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ret = PTR_ERR(clk);
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goto out_unmap;
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}
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pclk = clk_get_rate(clk);
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if (of_device_is_compatible(node, "moxa,moxart-timer")) {
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timer->t1_enable_val = MOXART_TIMER1_ENABLE;
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timer->t1_disable_val = MOXART_TIMER1_DISABLE;
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} else if (of_device_is_compatible(node, "aspeed,ast2400-timer")) {
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timer->t1_enable_val = ASPEED_TIMER1_ENABLE;
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timer->t1_disable_val = ASPEED_TIMER1_DISABLE;
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} else {
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pr_err("%s: unknown platform\n", node->full_name);
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ret = -EINVAL;
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goto out_unmap;
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}
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timer->count_per_tick = DIV_ROUND_CLOSEST(pclk, HZ);
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timer->clkevt.name = node->name;
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timer->clkevt.rating = 200;
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timer->clkevt.features = CLOCK_EVT_FEAT_PERIODIC |
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CLOCK_EVT_FEAT_ONESHOT;
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timer->clkevt.set_state_shutdown = moxart_shutdown;
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timer->clkevt.set_state_periodic = moxart_set_periodic;
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timer->clkevt.set_state_oneshot = moxart_set_oneshot;
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timer->clkevt.tick_resume = moxart_set_oneshot;
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timer->clkevt.set_next_event = moxart_clkevt_next_event;
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timer->clkevt.cpumask = cpumask_of(0);
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timer->clkevt.irq = irq;
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ret = clocksource_mmio_init(timer->base + TIMER2_BASE + REG_COUNT,
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"moxart_timer", pclk, 200, 32,
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clocksource_mmio_readl_down);
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if (ret) {
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pr_err("%s: clocksource_mmio_init failed\n", node->full_name);
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goto out_unmap;
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}
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ret = request_irq(irq, moxart_timer_interrupt, IRQF_TIMER,
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node->name, &timer->clkevt);
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if (ret) {
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pr_err("%s: setup_irq failed\n", node->full_name);
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goto out_unmap;
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}
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/* Clear match registers */
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writel(0, timer->base + TIMER1_BASE + REG_MATCH1);
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writel(0, timer->base + TIMER1_BASE + REG_MATCH2);
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writel(0, timer->base + TIMER2_BASE + REG_MATCH1);
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writel(0, timer->base + TIMER2_BASE + REG_MATCH2);
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/*
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* Start timer 2 rolling as our main wall clock source, keep timer 1
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* disabled
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*/
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writel(0, timer->base + TIMER_CR);
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writel(~0, timer->base + TIMER2_BASE + REG_LOAD);
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writel(timer->t1_disable_val, timer->base + TIMER_CR);
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/*
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* documentation is not publicly available:
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* min_delta / max_delta obtained by trial-and-error,
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* max_delta 0xfffffffe should be ok because count
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* register size is u32
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*/
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clockevents_config_and_register(&timer->clkevt, pclk, 0x4, 0xfffffffe);
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return 0;
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out_unmap:
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iounmap(timer->base);
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out_free:
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kfree(timer);
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return ret;
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}
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CLOCKSOURCE_OF_DECLARE(moxart, "moxa,moxart-timer", moxart_timer_init);
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CLOCKSOURCE_OF_DECLARE(aspeed, "aspeed,ast2400-timer", moxart_timer_init);
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