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![Bjorn Helgaas](/assets/img/avatar_default.png)
Hardware that supports only 32-bit config writes is not spec-compliant. For example, if software performs a 16-bit write, we must do a 32-bit read, merge in the 16 bits we intend to write, followed by a 32-bit write. If the 16 bits we *don't* intend to write happen to have any RW1C (write-one- to-clear) bits set, we just inadvertently cleared something we shouldn't have. Add a rate-limited warning when we do sub-32 bit config writes. Remove similar probe-time warnings from some of the affected host bridge drivers. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Enthusiastically-Acked-by: Russell King <rmk+kernel@armlinux.org.uk> Acked-by: Shawn Lin <shawn.lin@rock-chips.com> # rockchip Acked-by: Thierry Reding <treding@nvidia.com>
891 lines
21 KiB
C
891 lines
21 KiB
C
#include <linux/delay.h>
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#include <linux/pci.h>
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#include <linux/module.h>
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#include <linux/sched.h>
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#include <linux/slab.h>
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#include <linux/ioport.h>
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#include <linux/wait.h>
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#include "pci.h"
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/*
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* This interrupt-safe spinlock protects all accesses to PCI
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* configuration space.
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*/
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DEFINE_RAW_SPINLOCK(pci_lock);
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/*
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* Wrappers for all PCI configuration access functions. They just check
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* alignment, do locking and call the low-level functions pointed to
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* by pci_dev->ops.
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*/
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#define PCI_byte_BAD 0
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#define PCI_word_BAD (pos & 1)
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#define PCI_dword_BAD (pos & 3)
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#define PCI_OP_READ(size, type, len) \
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int pci_bus_read_config_##size \
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(struct pci_bus *bus, unsigned int devfn, int pos, type *value) \
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{ \
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int res; \
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unsigned long flags; \
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u32 data = 0; \
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if (PCI_##size##_BAD) return PCIBIOS_BAD_REGISTER_NUMBER; \
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raw_spin_lock_irqsave(&pci_lock, flags); \
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res = bus->ops->read(bus, devfn, pos, len, &data); \
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*value = (type)data; \
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raw_spin_unlock_irqrestore(&pci_lock, flags); \
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return res; \
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}
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#define PCI_OP_WRITE(size, type, len) \
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int pci_bus_write_config_##size \
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(struct pci_bus *bus, unsigned int devfn, int pos, type value) \
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{ \
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int res; \
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unsigned long flags; \
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if (PCI_##size##_BAD) return PCIBIOS_BAD_REGISTER_NUMBER; \
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raw_spin_lock_irqsave(&pci_lock, flags); \
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res = bus->ops->write(bus, devfn, pos, len, value); \
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raw_spin_unlock_irqrestore(&pci_lock, flags); \
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return res; \
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}
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PCI_OP_READ(byte, u8, 1)
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PCI_OP_READ(word, u16, 2)
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PCI_OP_READ(dword, u32, 4)
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PCI_OP_WRITE(byte, u8, 1)
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PCI_OP_WRITE(word, u16, 2)
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PCI_OP_WRITE(dword, u32, 4)
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EXPORT_SYMBOL(pci_bus_read_config_byte);
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EXPORT_SYMBOL(pci_bus_read_config_word);
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EXPORT_SYMBOL(pci_bus_read_config_dword);
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EXPORT_SYMBOL(pci_bus_write_config_byte);
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EXPORT_SYMBOL(pci_bus_write_config_word);
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EXPORT_SYMBOL(pci_bus_write_config_dword);
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int pci_generic_config_read(struct pci_bus *bus, unsigned int devfn,
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int where, int size, u32 *val)
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{
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void __iomem *addr;
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addr = bus->ops->map_bus(bus, devfn, where);
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if (!addr) {
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*val = ~0;
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return PCIBIOS_DEVICE_NOT_FOUND;
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}
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if (size == 1)
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*val = readb(addr);
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else if (size == 2)
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*val = readw(addr);
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else
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*val = readl(addr);
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return PCIBIOS_SUCCESSFUL;
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}
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EXPORT_SYMBOL_GPL(pci_generic_config_read);
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int pci_generic_config_write(struct pci_bus *bus, unsigned int devfn,
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int where, int size, u32 val)
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{
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void __iomem *addr;
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addr = bus->ops->map_bus(bus, devfn, where);
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if (!addr)
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return PCIBIOS_DEVICE_NOT_FOUND;
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if (size == 1)
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writeb(val, addr);
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else if (size == 2)
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writew(val, addr);
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else
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writel(val, addr);
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return PCIBIOS_SUCCESSFUL;
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}
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EXPORT_SYMBOL_GPL(pci_generic_config_write);
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int pci_generic_config_read32(struct pci_bus *bus, unsigned int devfn,
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int where, int size, u32 *val)
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{
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void __iomem *addr;
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addr = bus->ops->map_bus(bus, devfn, where & ~0x3);
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if (!addr) {
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*val = ~0;
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return PCIBIOS_DEVICE_NOT_FOUND;
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}
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*val = readl(addr);
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if (size <= 2)
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*val = (*val >> (8 * (where & 3))) & ((1 << (size * 8)) - 1);
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return PCIBIOS_SUCCESSFUL;
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}
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EXPORT_SYMBOL_GPL(pci_generic_config_read32);
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int pci_generic_config_write32(struct pci_bus *bus, unsigned int devfn,
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int where, int size, u32 val)
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{
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void __iomem *addr;
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u32 mask, tmp;
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addr = bus->ops->map_bus(bus, devfn, where & ~0x3);
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if (!addr)
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return PCIBIOS_DEVICE_NOT_FOUND;
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if (size == 4) {
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writel(val, addr);
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return PCIBIOS_SUCCESSFUL;
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}
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/*
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* In general, hardware that supports only 32-bit writes on PCI is
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* not spec-compliant. For example, software may perform a 16-bit
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* write. If the hardware only supports 32-bit accesses, we must
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* do a 32-bit read, merge in the 16 bits we intend to write,
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* followed by a 32-bit write. If the 16 bits we *don't* intend to
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* write happen to have any RW1C (write-one-to-clear) bits set, we
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* just inadvertently cleared something we shouldn't have.
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*/
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dev_warn_ratelimited(&bus->dev, "%d-byte config write to %04x:%02x:%02x.%d offset %#x may corrupt adjacent RW1C bits\n",
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size, pci_domain_nr(bus), bus->number,
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PCI_SLOT(devfn), PCI_FUNC(devfn), where);
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mask = ~(((1 << (size * 8)) - 1) << ((where & 0x3) * 8));
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tmp = readl(addr) & mask;
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tmp |= val << ((where & 0x3) * 8);
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writel(tmp, addr);
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return PCIBIOS_SUCCESSFUL;
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}
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EXPORT_SYMBOL_GPL(pci_generic_config_write32);
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/**
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* pci_bus_set_ops - Set raw operations of pci bus
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* @bus: pci bus struct
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* @ops: new raw operations
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*
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* Return previous raw operations
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*/
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struct pci_ops *pci_bus_set_ops(struct pci_bus *bus, struct pci_ops *ops)
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{
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struct pci_ops *old_ops;
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unsigned long flags;
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raw_spin_lock_irqsave(&pci_lock, flags);
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old_ops = bus->ops;
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bus->ops = ops;
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raw_spin_unlock_irqrestore(&pci_lock, flags);
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return old_ops;
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}
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EXPORT_SYMBOL(pci_bus_set_ops);
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/*
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* The following routines are to prevent the user from accessing PCI config
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* space when it's unsafe to do so. Some devices require this during BIST and
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* we're required to prevent it during D-state transitions.
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*
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* We have a bit per device to indicate it's blocked and a global wait queue
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* for callers to sleep on until devices are unblocked.
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*/
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static DECLARE_WAIT_QUEUE_HEAD(pci_cfg_wait);
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static noinline void pci_wait_cfg(struct pci_dev *dev)
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{
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DECLARE_WAITQUEUE(wait, current);
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__add_wait_queue(&pci_cfg_wait, &wait);
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do {
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set_current_state(TASK_UNINTERRUPTIBLE);
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raw_spin_unlock_irq(&pci_lock);
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schedule();
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raw_spin_lock_irq(&pci_lock);
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} while (dev->block_cfg_access);
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__remove_wait_queue(&pci_cfg_wait, &wait);
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}
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/* Returns 0 on success, negative values indicate error. */
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#define PCI_USER_READ_CONFIG(size, type) \
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int pci_user_read_config_##size \
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(struct pci_dev *dev, int pos, type *val) \
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{ \
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int ret = PCIBIOS_SUCCESSFUL; \
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u32 data = -1; \
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if (PCI_##size##_BAD) \
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return -EINVAL; \
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raw_spin_lock_irq(&pci_lock); \
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if (unlikely(dev->block_cfg_access)) \
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pci_wait_cfg(dev); \
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ret = dev->bus->ops->read(dev->bus, dev->devfn, \
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pos, sizeof(type), &data); \
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raw_spin_unlock_irq(&pci_lock); \
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*val = (type)data; \
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return pcibios_err_to_errno(ret); \
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} \
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EXPORT_SYMBOL_GPL(pci_user_read_config_##size);
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/* Returns 0 on success, negative values indicate error. */
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#define PCI_USER_WRITE_CONFIG(size, type) \
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int pci_user_write_config_##size \
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(struct pci_dev *dev, int pos, type val) \
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{ \
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int ret = PCIBIOS_SUCCESSFUL; \
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if (PCI_##size##_BAD) \
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return -EINVAL; \
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raw_spin_lock_irq(&pci_lock); \
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if (unlikely(dev->block_cfg_access)) \
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pci_wait_cfg(dev); \
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ret = dev->bus->ops->write(dev->bus, dev->devfn, \
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pos, sizeof(type), val); \
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raw_spin_unlock_irq(&pci_lock); \
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return pcibios_err_to_errno(ret); \
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} \
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EXPORT_SYMBOL_GPL(pci_user_write_config_##size);
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PCI_USER_READ_CONFIG(byte, u8)
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PCI_USER_READ_CONFIG(word, u16)
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PCI_USER_READ_CONFIG(dword, u32)
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PCI_USER_WRITE_CONFIG(byte, u8)
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PCI_USER_WRITE_CONFIG(word, u16)
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PCI_USER_WRITE_CONFIG(dword, u32)
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/* VPD access through PCI 2.2+ VPD capability */
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/**
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* pci_read_vpd - Read one entry from Vital Product Data
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* @dev: pci device struct
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* @pos: offset in vpd space
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* @count: number of bytes to read
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* @buf: pointer to where to store result
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*/
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ssize_t pci_read_vpd(struct pci_dev *dev, loff_t pos, size_t count, void *buf)
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{
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if (!dev->vpd || !dev->vpd->ops)
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return -ENODEV;
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return dev->vpd->ops->read(dev, pos, count, buf);
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}
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EXPORT_SYMBOL(pci_read_vpd);
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/**
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* pci_write_vpd - Write entry to Vital Product Data
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* @dev: pci device struct
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* @pos: offset in vpd space
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* @count: number of bytes to write
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* @buf: buffer containing write data
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*/
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ssize_t pci_write_vpd(struct pci_dev *dev, loff_t pos, size_t count, const void *buf)
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{
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if (!dev->vpd || !dev->vpd->ops)
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return -ENODEV;
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return dev->vpd->ops->write(dev, pos, count, buf);
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}
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EXPORT_SYMBOL(pci_write_vpd);
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/**
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* pci_set_vpd_size - Set size of Vital Product Data space
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* @dev: pci device struct
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* @len: size of vpd space
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*/
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int pci_set_vpd_size(struct pci_dev *dev, size_t len)
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{
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if (!dev->vpd || !dev->vpd->ops)
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return -ENODEV;
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return dev->vpd->ops->set_size(dev, len);
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}
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EXPORT_SYMBOL(pci_set_vpd_size);
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#define PCI_VPD_MAX_SIZE (PCI_VPD_ADDR_MASK + 1)
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/**
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* pci_vpd_size - determine actual size of Vital Product Data
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* @dev: pci device struct
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* @old_size: current assumed size, also maximum allowed size
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*/
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static size_t pci_vpd_size(struct pci_dev *dev, size_t old_size)
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{
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size_t off = 0;
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unsigned char header[1+2]; /* 1 byte tag, 2 bytes length */
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while (off < old_size &&
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pci_read_vpd(dev, off, 1, header) == 1) {
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unsigned char tag;
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if (header[0] & PCI_VPD_LRDT) {
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/* Large Resource Data Type Tag */
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tag = pci_vpd_lrdt_tag(header);
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/* Only read length from known tag items */
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if ((tag == PCI_VPD_LTIN_ID_STRING) ||
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(tag == PCI_VPD_LTIN_RO_DATA) ||
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(tag == PCI_VPD_LTIN_RW_DATA)) {
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if (pci_read_vpd(dev, off+1, 2,
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&header[1]) != 2) {
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dev_warn(&dev->dev,
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"invalid large VPD tag %02x size at offset %zu",
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tag, off + 1);
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return 0;
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}
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off += PCI_VPD_LRDT_TAG_SIZE +
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pci_vpd_lrdt_size(header);
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}
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} else {
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/* Short Resource Data Type Tag */
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off += PCI_VPD_SRDT_TAG_SIZE +
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pci_vpd_srdt_size(header);
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tag = pci_vpd_srdt_tag(header);
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}
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if (tag == PCI_VPD_STIN_END) /* End tag descriptor */
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return off;
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if ((tag != PCI_VPD_LTIN_ID_STRING) &&
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(tag != PCI_VPD_LTIN_RO_DATA) &&
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(tag != PCI_VPD_LTIN_RW_DATA)) {
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dev_warn(&dev->dev,
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"invalid %s VPD tag %02x at offset %zu",
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(header[0] & PCI_VPD_LRDT) ? "large" : "short",
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tag, off);
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return 0;
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}
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}
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return 0;
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}
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/*
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* Wait for last operation to complete.
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* This code has to spin since there is no other notification from the PCI
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* hardware. Since the VPD is often implemented by serial attachment to an
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* EEPROM, it may take many milliseconds to complete.
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*
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* Returns 0 on success, negative values indicate error.
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*/
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static int pci_vpd_wait(struct pci_dev *dev)
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{
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struct pci_vpd *vpd = dev->vpd;
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unsigned long timeout = jiffies + msecs_to_jiffies(50);
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unsigned long max_sleep = 16;
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u16 status;
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int ret;
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if (!vpd->busy)
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return 0;
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while (time_before(jiffies, timeout)) {
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ret = pci_user_read_config_word(dev, vpd->cap + PCI_VPD_ADDR,
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&status);
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if (ret < 0)
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return ret;
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if ((status & PCI_VPD_ADDR_F) == vpd->flag) {
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vpd->busy = 0;
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return 0;
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}
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if (fatal_signal_pending(current))
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return -EINTR;
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usleep_range(10, max_sleep);
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if (max_sleep < 1024)
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max_sleep *= 2;
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}
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dev_warn(&dev->dev, "VPD access failed. This is likely a firmware bug on this device. Contact the card vendor for a firmware update\n");
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return -ETIMEDOUT;
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}
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static ssize_t pci_vpd_read(struct pci_dev *dev, loff_t pos, size_t count,
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void *arg)
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{
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struct pci_vpd *vpd = dev->vpd;
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int ret;
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loff_t end = pos + count;
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u8 *buf = arg;
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if (pos < 0)
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return -EINVAL;
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if (!vpd->valid) {
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vpd->valid = 1;
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vpd->len = pci_vpd_size(dev, vpd->len);
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}
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if (vpd->len == 0)
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return -EIO;
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if (pos > vpd->len)
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return 0;
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if (end > vpd->len) {
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end = vpd->len;
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count = end - pos;
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}
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if (mutex_lock_killable(&vpd->lock))
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return -EINTR;
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ret = pci_vpd_wait(dev);
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if (ret < 0)
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goto out;
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while (pos < end) {
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u32 val;
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unsigned int i, skip;
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ret = pci_user_write_config_word(dev, vpd->cap + PCI_VPD_ADDR,
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pos & ~3);
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if (ret < 0)
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break;
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vpd->busy = 1;
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vpd->flag = PCI_VPD_ADDR_F;
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ret = pci_vpd_wait(dev);
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if (ret < 0)
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break;
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ret = pci_user_read_config_dword(dev, vpd->cap + PCI_VPD_DATA, &val);
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if (ret < 0)
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break;
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skip = pos & 3;
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for (i = 0; i < sizeof(u32); i++) {
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if (i >= skip) {
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*buf++ = val;
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if (++pos == end)
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break;
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}
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val >>= 8;
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}
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}
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out:
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mutex_unlock(&vpd->lock);
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return ret ? ret : count;
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}
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static ssize_t pci_vpd_write(struct pci_dev *dev, loff_t pos, size_t count,
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const void *arg)
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{
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struct pci_vpd *vpd = dev->vpd;
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const u8 *buf = arg;
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loff_t end = pos + count;
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int ret = 0;
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if (pos < 0 || (pos & 3) || (count & 3))
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return -EINVAL;
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if (!vpd->valid) {
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vpd->valid = 1;
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vpd->len = pci_vpd_size(dev, vpd->len);
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}
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if (vpd->len == 0)
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return -EIO;
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|
|
if (end > vpd->len)
|
|
return -EINVAL;
|
|
|
|
if (mutex_lock_killable(&vpd->lock))
|
|
return -EINTR;
|
|
|
|
ret = pci_vpd_wait(dev);
|
|
if (ret < 0)
|
|
goto out;
|
|
|
|
while (pos < end) {
|
|
u32 val;
|
|
|
|
val = *buf++;
|
|
val |= *buf++ << 8;
|
|
val |= *buf++ << 16;
|
|
val |= *buf++ << 24;
|
|
|
|
ret = pci_user_write_config_dword(dev, vpd->cap + PCI_VPD_DATA, val);
|
|
if (ret < 0)
|
|
break;
|
|
ret = pci_user_write_config_word(dev, vpd->cap + PCI_VPD_ADDR,
|
|
pos | PCI_VPD_ADDR_F);
|
|
if (ret < 0)
|
|
break;
|
|
|
|
vpd->busy = 1;
|
|
vpd->flag = 0;
|
|
ret = pci_vpd_wait(dev);
|
|
if (ret < 0)
|
|
break;
|
|
|
|
pos += sizeof(u32);
|
|
}
|
|
out:
|
|
mutex_unlock(&vpd->lock);
|
|
return ret ? ret : count;
|
|
}
|
|
|
|
static int pci_vpd_set_size(struct pci_dev *dev, size_t len)
|
|
{
|
|
struct pci_vpd *vpd = dev->vpd;
|
|
|
|
if (len == 0 || len > PCI_VPD_MAX_SIZE)
|
|
return -EIO;
|
|
|
|
vpd->valid = 1;
|
|
vpd->len = len;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct pci_vpd_ops pci_vpd_ops = {
|
|
.read = pci_vpd_read,
|
|
.write = pci_vpd_write,
|
|
.set_size = pci_vpd_set_size,
|
|
};
|
|
|
|
static ssize_t pci_vpd_f0_read(struct pci_dev *dev, loff_t pos, size_t count,
|
|
void *arg)
|
|
{
|
|
struct pci_dev *tdev = pci_get_slot(dev->bus,
|
|
PCI_DEVFN(PCI_SLOT(dev->devfn), 0));
|
|
ssize_t ret;
|
|
|
|
if (!tdev)
|
|
return -ENODEV;
|
|
|
|
ret = pci_read_vpd(tdev, pos, count, arg);
|
|
pci_dev_put(tdev);
|
|
return ret;
|
|
}
|
|
|
|
static ssize_t pci_vpd_f0_write(struct pci_dev *dev, loff_t pos, size_t count,
|
|
const void *arg)
|
|
{
|
|
struct pci_dev *tdev = pci_get_slot(dev->bus,
|
|
PCI_DEVFN(PCI_SLOT(dev->devfn), 0));
|
|
ssize_t ret;
|
|
|
|
if (!tdev)
|
|
return -ENODEV;
|
|
|
|
ret = pci_write_vpd(tdev, pos, count, arg);
|
|
pci_dev_put(tdev);
|
|
return ret;
|
|
}
|
|
|
|
static int pci_vpd_f0_set_size(struct pci_dev *dev, size_t len)
|
|
{
|
|
struct pci_dev *tdev = pci_get_slot(dev->bus,
|
|
PCI_DEVFN(PCI_SLOT(dev->devfn), 0));
|
|
int ret;
|
|
|
|
if (!tdev)
|
|
return -ENODEV;
|
|
|
|
ret = pci_set_vpd_size(tdev, len);
|
|
pci_dev_put(tdev);
|
|
return ret;
|
|
}
|
|
|
|
static const struct pci_vpd_ops pci_vpd_f0_ops = {
|
|
.read = pci_vpd_f0_read,
|
|
.write = pci_vpd_f0_write,
|
|
.set_size = pci_vpd_f0_set_size,
|
|
};
|
|
|
|
int pci_vpd_init(struct pci_dev *dev)
|
|
{
|
|
struct pci_vpd *vpd;
|
|
u8 cap;
|
|
|
|
cap = pci_find_capability(dev, PCI_CAP_ID_VPD);
|
|
if (!cap)
|
|
return -ENODEV;
|
|
|
|
vpd = kzalloc(sizeof(*vpd), GFP_ATOMIC);
|
|
if (!vpd)
|
|
return -ENOMEM;
|
|
|
|
vpd->len = PCI_VPD_MAX_SIZE;
|
|
if (dev->dev_flags & PCI_DEV_FLAGS_VPD_REF_F0)
|
|
vpd->ops = &pci_vpd_f0_ops;
|
|
else
|
|
vpd->ops = &pci_vpd_ops;
|
|
mutex_init(&vpd->lock);
|
|
vpd->cap = cap;
|
|
vpd->busy = 0;
|
|
vpd->valid = 0;
|
|
dev->vpd = vpd;
|
|
return 0;
|
|
}
|
|
|
|
void pci_vpd_release(struct pci_dev *dev)
|
|
{
|
|
kfree(dev->vpd);
|
|
}
|
|
|
|
/**
|
|
* pci_cfg_access_lock - Lock PCI config reads/writes
|
|
* @dev: pci device struct
|
|
*
|
|
* When access is locked, any userspace reads or writes to config
|
|
* space and concurrent lock requests will sleep until access is
|
|
* allowed via pci_cfg_access_unlocked again.
|
|
*/
|
|
void pci_cfg_access_lock(struct pci_dev *dev)
|
|
{
|
|
might_sleep();
|
|
|
|
raw_spin_lock_irq(&pci_lock);
|
|
if (dev->block_cfg_access)
|
|
pci_wait_cfg(dev);
|
|
dev->block_cfg_access = 1;
|
|
raw_spin_unlock_irq(&pci_lock);
|
|
}
|
|
EXPORT_SYMBOL_GPL(pci_cfg_access_lock);
|
|
|
|
/**
|
|
* pci_cfg_access_trylock - try to lock PCI config reads/writes
|
|
* @dev: pci device struct
|
|
*
|
|
* Same as pci_cfg_access_lock, but will return 0 if access is
|
|
* already locked, 1 otherwise. This function can be used from
|
|
* atomic contexts.
|
|
*/
|
|
bool pci_cfg_access_trylock(struct pci_dev *dev)
|
|
{
|
|
unsigned long flags;
|
|
bool locked = true;
|
|
|
|
raw_spin_lock_irqsave(&pci_lock, flags);
|
|
if (dev->block_cfg_access)
|
|
locked = false;
|
|
else
|
|
dev->block_cfg_access = 1;
|
|
raw_spin_unlock_irqrestore(&pci_lock, flags);
|
|
|
|
return locked;
|
|
}
|
|
EXPORT_SYMBOL_GPL(pci_cfg_access_trylock);
|
|
|
|
/**
|
|
* pci_cfg_access_unlock - Unlock PCI config reads/writes
|
|
* @dev: pci device struct
|
|
*
|
|
* This function allows PCI config accesses to resume.
|
|
*/
|
|
void pci_cfg_access_unlock(struct pci_dev *dev)
|
|
{
|
|
unsigned long flags;
|
|
|
|
raw_spin_lock_irqsave(&pci_lock, flags);
|
|
|
|
/* This indicates a problem in the caller, but we don't need
|
|
* to kill them, unlike a double-block above. */
|
|
WARN_ON(!dev->block_cfg_access);
|
|
|
|
dev->block_cfg_access = 0;
|
|
wake_up_all(&pci_cfg_wait);
|
|
raw_spin_unlock_irqrestore(&pci_lock, flags);
|
|
}
|
|
EXPORT_SYMBOL_GPL(pci_cfg_access_unlock);
|
|
|
|
static inline int pcie_cap_version(const struct pci_dev *dev)
|
|
{
|
|
return pcie_caps_reg(dev) & PCI_EXP_FLAGS_VERS;
|
|
}
|
|
|
|
static bool pcie_downstream_port(const struct pci_dev *dev)
|
|
{
|
|
int type = pci_pcie_type(dev);
|
|
|
|
return type == PCI_EXP_TYPE_ROOT_PORT ||
|
|
type == PCI_EXP_TYPE_DOWNSTREAM;
|
|
}
|
|
|
|
bool pcie_cap_has_lnkctl(const struct pci_dev *dev)
|
|
{
|
|
int type = pci_pcie_type(dev);
|
|
|
|
return type == PCI_EXP_TYPE_ENDPOINT ||
|
|
type == PCI_EXP_TYPE_LEG_END ||
|
|
type == PCI_EXP_TYPE_ROOT_PORT ||
|
|
type == PCI_EXP_TYPE_UPSTREAM ||
|
|
type == PCI_EXP_TYPE_DOWNSTREAM ||
|
|
type == PCI_EXP_TYPE_PCI_BRIDGE ||
|
|
type == PCI_EXP_TYPE_PCIE_BRIDGE;
|
|
}
|
|
|
|
static inline bool pcie_cap_has_sltctl(const struct pci_dev *dev)
|
|
{
|
|
return pcie_downstream_port(dev) &&
|
|
pcie_caps_reg(dev) & PCI_EXP_FLAGS_SLOT;
|
|
}
|
|
|
|
static inline bool pcie_cap_has_rtctl(const struct pci_dev *dev)
|
|
{
|
|
int type = pci_pcie_type(dev);
|
|
|
|
return type == PCI_EXP_TYPE_ROOT_PORT ||
|
|
type == PCI_EXP_TYPE_RC_EC;
|
|
}
|
|
|
|
static bool pcie_capability_reg_implemented(struct pci_dev *dev, int pos)
|
|
{
|
|
if (!pci_is_pcie(dev))
|
|
return false;
|
|
|
|
switch (pos) {
|
|
case PCI_EXP_FLAGS:
|
|
return true;
|
|
case PCI_EXP_DEVCAP:
|
|
case PCI_EXP_DEVCTL:
|
|
case PCI_EXP_DEVSTA:
|
|
return true;
|
|
case PCI_EXP_LNKCAP:
|
|
case PCI_EXP_LNKCTL:
|
|
case PCI_EXP_LNKSTA:
|
|
return pcie_cap_has_lnkctl(dev);
|
|
case PCI_EXP_SLTCAP:
|
|
case PCI_EXP_SLTCTL:
|
|
case PCI_EXP_SLTSTA:
|
|
return pcie_cap_has_sltctl(dev);
|
|
case PCI_EXP_RTCTL:
|
|
case PCI_EXP_RTCAP:
|
|
case PCI_EXP_RTSTA:
|
|
return pcie_cap_has_rtctl(dev);
|
|
case PCI_EXP_DEVCAP2:
|
|
case PCI_EXP_DEVCTL2:
|
|
case PCI_EXP_LNKCAP2:
|
|
case PCI_EXP_LNKCTL2:
|
|
case PCI_EXP_LNKSTA2:
|
|
return pcie_cap_version(dev) > 1;
|
|
default:
|
|
return false;
|
|
}
|
|
}
|
|
|
|
/*
|
|
* Note that these accessor functions are only for the "PCI Express
|
|
* Capability" (see PCIe spec r3.0, sec 7.8). They do not apply to the
|
|
* other "PCI Express Extended Capabilities" (AER, VC, ACS, MFVC, etc.)
|
|
*/
|
|
int pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *val)
|
|
{
|
|
int ret;
|
|
|
|
*val = 0;
|
|
if (pos & 1)
|
|
return -EINVAL;
|
|
|
|
if (pcie_capability_reg_implemented(dev, pos)) {
|
|
ret = pci_read_config_word(dev, pci_pcie_cap(dev) + pos, val);
|
|
/*
|
|
* Reset *val to 0 if pci_read_config_word() fails, it may
|
|
* have been written as 0xFFFF if hardware error happens
|
|
* during pci_read_config_word().
|
|
*/
|
|
if (ret)
|
|
*val = 0;
|
|
return ret;
|
|
}
|
|
|
|
/*
|
|
* For Functions that do not implement the Slot Capabilities,
|
|
* Slot Status, and Slot Control registers, these spaces must
|
|
* be hardwired to 0b, with the exception of the Presence Detect
|
|
* State bit in the Slot Status register of Downstream Ports,
|
|
* which must be hardwired to 1b. (PCIe Base Spec 3.0, sec 7.8)
|
|
*/
|
|
if (pci_is_pcie(dev) && pcie_downstream_port(dev) &&
|
|
pos == PCI_EXP_SLTSTA)
|
|
*val = PCI_EXP_SLTSTA_PDS;
|
|
|
|
return 0;
|
|
}
|
|
EXPORT_SYMBOL(pcie_capability_read_word);
|
|
|
|
int pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *val)
|
|
{
|
|
int ret;
|
|
|
|
*val = 0;
|
|
if (pos & 3)
|
|
return -EINVAL;
|
|
|
|
if (pcie_capability_reg_implemented(dev, pos)) {
|
|
ret = pci_read_config_dword(dev, pci_pcie_cap(dev) + pos, val);
|
|
/*
|
|
* Reset *val to 0 if pci_read_config_dword() fails, it may
|
|
* have been written as 0xFFFFFFFF if hardware error happens
|
|
* during pci_read_config_dword().
|
|
*/
|
|
if (ret)
|
|
*val = 0;
|
|
return ret;
|
|
}
|
|
|
|
if (pci_is_pcie(dev) && pcie_downstream_port(dev) &&
|
|
pos == PCI_EXP_SLTSTA)
|
|
*val = PCI_EXP_SLTSTA_PDS;
|
|
|
|
return 0;
|
|
}
|
|
EXPORT_SYMBOL(pcie_capability_read_dword);
|
|
|
|
int pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val)
|
|
{
|
|
if (pos & 1)
|
|
return -EINVAL;
|
|
|
|
if (!pcie_capability_reg_implemented(dev, pos))
|
|
return 0;
|
|
|
|
return pci_write_config_word(dev, pci_pcie_cap(dev) + pos, val);
|
|
}
|
|
EXPORT_SYMBOL(pcie_capability_write_word);
|
|
|
|
int pcie_capability_write_dword(struct pci_dev *dev, int pos, u32 val)
|
|
{
|
|
if (pos & 3)
|
|
return -EINVAL;
|
|
|
|
if (!pcie_capability_reg_implemented(dev, pos))
|
|
return 0;
|
|
|
|
return pci_write_config_dword(dev, pci_pcie_cap(dev) + pos, val);
|
|
}
|
|
EXPORT_SYMBOL(pcie_capability_write_dword);
|
|
|
|
int pcie_capability_clear_and_set_word(struct pci_dev *dev, int pos,
|
|
u16 clear, u16 set)
|
|
{
|
|
int ret;
|
|
u16 val;
|
|
|
|
ret = pcie_capability_read_word(dev, pos, &val);
|
|
if (!ret) {
|
|
val &= ~clear;
|
|
val |= set;
|
|
ret = pcie_capability_write_word(dev, pos, val);
|
|
}
|
|
|
|
return ret;
|
|
}
|
|
EXPORT_SYMBOL(pcie_capability_clear_and_set_word);
|
|
|
|
int pcie_capability_clear_and_set_dword(struct pci_dev *dev, int pos,
|
|
u32 clear, u32 set)
|
|
{
|
|
int ret;
|
|
u32 val;
|
|
|
|
ret = pcie_capability_read_dword(dev, pos, &val);
|
|
if (!ret) {
|
|
val &= ~clear;
|
|
val |= set;
|
|
ret = pcie_capability_write_dword(dev, pos, val);
|
|
}
|
|
|
|
return ret;
|
|
}
|
|
EXPORT_SYMBOL(pcie_capability_clear_and_set_dword);
|