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![Javier Martinez Canillas](/assets/img/avatar_default.png)
The watchdog maximum timeout value is determined by the number of bits for the interval timer counter, its source clock frequency, the number of bits of the prescaler and maximum divider value. This can be calculated with the following equation: max_timeout = counter / (freq / (max_prescale + 1) / max_divider) Setting a maximum timeout value will allow the watchdog core to refuse user-space calls to the WDIOC_SETTIMEOUT ioctl that sets not supported timeout values. For example, systemd tries to set a timeout of 10 minutes on reboot to ensure that the machine will be rebooted even if a reboot failed. This leads to the following error message on an Exynos5422 Odroid XU4 board: [ 147.986045] s3c2410-wdt 101d0000.watchdog: timeout 600 too big Reported-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Signed-off-by: Javier Martinez Canillas <javier@osg.samsung.com> Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Signed-off-by: Guenter Roeck <linux@roeck-us.net> Signed-off-by: Wim Van Sebroeck <wim@iguana.be>
763 lines
20 KiB
C
763 lines
20 KiB
C
/* linux/drivers/char/watchdog/s3c2410_wdt.c
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*
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* Copyright (c) 2004 Simtec Electronics
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* Ben Dooks <ben@simtec.co.uk>
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*
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* S3C2410 Watchdog Timer Support
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*
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* Based on, softdog.c by Alan Cox,
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* (c) Copyright 1996 Alan Cox <alan@lxorguk.ukuu.org.uk>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
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#include <linux/module.h>
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#include <linux/moduleparam.h>
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#include <linux/types.h>
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#include <linux/timer.h>
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#include <linux/watchdog.h>
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#include <linux/platform_device.h>
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#include <linux/interrupt.h>
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#include <linux/clk.h>
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#include <linux/uaccess.h>
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#include <linux/io.h>
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#include <linux/cpufreq.h>
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#include <linux/slab.h>
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#include <linux/err.h>
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#include <linux/of.h>
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#include <linux/mfd/syscon.h>
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#include <linux/regmap.h>
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#include <linux/delay.h>
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#define S3C2410_WTCON 0x00
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#define S3C2410_WTDAT 0x04
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#define S3C2410_WTCNT 0x08
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#define S3C2410_WTCNT_MAXCNT 0xffff
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#define S3C2410_WTCON_RSTEN (1 << 0)
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#define S3C2410_WTCON_INTEN (1 << 2)
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#define S3C2410_WTCON_ENABLE (1 << 5)
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#define S3C2410_WTCON_DIV16 (0 << 3)
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#define S3C2410_WTCON_DIV32 (1 << 3)
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#define S3C2410_WTCON_DIV64 (2 << 3)
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#define S3C2410_WTCON_DIV128 (3 << 3)
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#define S3C2410_WTCON_MAXDIV 0x80
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#define S3C2410_WTCON_PRESCALE(x) ((x) << 8)
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#define S3C2410_WTCON_PRESCALE_MASK (0xff << 8)
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#define S3C2410_WTCON_PRESCALE_MAX 0xff
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#define CONFIG_S3C2410_WATCHDOG_ATBOOT (0)
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#define CONFIG_S3C2410_WATCHDOG_DEFAULT_TIME (15)
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#define EXYNOS5_RST_STAT_REG_OFFSET 0x0404
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#define EXYNOS5_WDT_DISABLE_REG_OFFSET 0x0408
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#define EXYNOS5_WDT_MASK_RESET_REG_OFFSET 0x040c
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#define QUIRK_HAS_PMU_CONFIG (1 << 0)
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#define QUIRK_HAS_RST_STAT (1 << 1)
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/* These quirks require that we have a PMU register map */
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#define QUIRKS_HAVE_PMUREG (QUIRK_HAS_PMU_CONFIG | \
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QUIRK_HAS_RST_STAT)
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static bool nowayout = WATCHDOG_NOWAYOUT;
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static int tmr_margin;
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static int tmr_atboot = CONFIG_S3C2410_WATCHDOG_ATBOOT;
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static int soft_noboot;
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static int debug;
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module_param(tmr_margin, int, 0);
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module_param(tmr_atboot, int, 0);
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module_param(nowayout, bool, 0);
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module_param(soft_noboot, int, 0);
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module_param(debug, int, 0);
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MODULE_PARM_DESC(tmr_margin, "Watchdog tmr_margin in seconds. (default="
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__MODULE_STRING(CONFIG_S3C2410_WATCHDOG_DEFAULT_TIME) ")");
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MODULE_PARM_DESC(tmr_atboot,
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"Watchdog is started at boot time if set to 1, default="
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__MODULE_STRING(CONFIG_S3C2410_WATCHDOG_ATBOOT));
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MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default="
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__MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
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MODULE_PARM_DESC(soft_noboot, "Watchdog action, set to 1 to ignore reboots, "
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"0 to reboot (default 0)");
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MODULE_PARM_DESC(debug, "Watchdog debug, set to >1 for debug (default 0)");
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/**
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* struct s3c2410_wdt_variant - Per-variant config data
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*
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* @disable_reg: Offset in pmureg for the register that disables the watchdog
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* timer reset functionality.
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* @mask_reset_reg: Offset in pmureg for the register that masks the watchdog
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* timer reset functionality.
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* @mask_bit: Bit number for the watchdog timer in the disable register and the
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* mask reset register.
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* @rst_stat_reg: Offset in pmureg for the register that has the reset status.
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* @rst_stat_bit: Bit number in the rst_stat register indicating a watchdog
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* reset.
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* @quirks: A bitfield of quirks.
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*/
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struct s3c2410_wdt_variant {
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int disable_reg;
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int mask_reset_reg;
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int mask_bit;
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int rst_stat_reg;
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int rst_stat_bit;
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u32 quirks;
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};
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struct s3c2410_wdt {
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struct device *dev;
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struct clk *clock;
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void __iomem *reg_base;
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unsigned int count;
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spinlock_t lock;
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unsigned long wtcon_save;
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unsigned long wtdat_save;
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struct watchdog_device wdt_device;
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struct notifier_block freq_transition;
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struct s3c2410_wdt_variant *drv_data;
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struct regmap *pmureg;
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};
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static const struct s3c2410_wdt_variant drv_data_s3c2410 = {
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.quirks = 0
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};
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#ifdef CONFIG_OF
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static const struct s3c2410_wdt_variant drv_data_exynos5250 = {
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.disable_reg = EXYNOS5_WDT_DISABLE_REG_OFFSET,
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.mask_reset_reg = EXYNOS5_WDT_MASK_RESET_REG_OFFSET,
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.mask_bit = 20,
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.rst_stat_reg = EXYNOS5_RST_STAT_REG_OFFSET,
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.rst_stat_bit = 20,
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.quirks = QUIRK_HAS_PMU_CONFIG | QUIRK_HAS_RST_STAT,
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};
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static const struct s3c2410_wdt_variant drv_data_exynos5420 = {
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.disable_reg = EXYNOS5_WDT_DISABLE_REG_OFFSET,
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.mask_reset_reg = EXYNOS5_WDT_MASK_RESET_REG_OFFSET,
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.mask_bit = 0,
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.rst_stat_reg = EXYNOS5_RST_STAT_REG_OFFSET,
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.rst_stat_bit = 9,
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.quirks = QUIRK_HAS_PMU_CONFIG | QUIRK_HAS_RST_STAT,
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};
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static const struct s3c2410_wdt_variant drv_data_exynos7 = {
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.disable_reg = EXYNOS5_WDT_DISABLE_REG_OFFSET,
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.mask_reset_reg = EXYNOS5_WDT_MASK_RESET_REG_OFFSET,
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.mask_bit = 23,
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.rst_stat_reg = EXYNOS5_RST_STAT_REG_OFFSET,
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.rst_stat_bit = 23, /* A57 WDTRESET */
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.quirks = QUIRK_HAS_PMU_CONFIG | QUIRK_HAS_RST_STAT,
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};
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static const struct of_device_id s3c2410_wdt_match[] = {
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{ .compatible = "samsung,s3c2410-wdt",
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.data = &drv_data_s3c2410 },
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{ .compatible = "samsung,exynos5250-wdt",
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.data = &drv_data_exynos5250 },
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{ .compatible = "samsung,exynos5420-wdt",
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.data = &drv_data_exynos5420 },
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{ .compatible = "samsung,exynos7-wdt",
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.data = &drv_data_exynos7 },
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{},
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};
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MODULE_DEVICE_TABLE(of, s3c2410_wdt_match);
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#endif
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static const struct platform_device_id s3c2410_wdt_ids[] = {
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{
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.name = "s3c2410-wdt",
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.driver_data = (unsigned long)&drv_data_s3c2410,
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},
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{}
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};
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MODULE_DEVICE_TABLE(platform, s3c2410_wdt_ids);
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/* watchdog control routines */
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#define DBG(fmt, ...) \
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do { \
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if (debug) \
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pr_info(fmt, ##__VA_ARGS__); \
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} while (0)
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/* functions */
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static inline unsigned int s3c2410wdt_max_timeout(struct clk *clock)
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{
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unsigned long freq = clk_get_rate(clock);
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return S3C2410_WTCNT_MAXCNT / (freq / (S3C2410_WTCON_PRESCALE_MAX + 1)
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/ S3C2410_WTCON_MAXDIV);
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}
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static inline struct s3c2410_wdt *freq_to_wdt(struct notifier_block *nb)
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{
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return container_of(nb, struct s3c2410_wdt, freq_transition);
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}
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static int s3c2410wdt_mask_and_disable_reset(struct s3c2410_wdt *wdt, bool mask)
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{
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int ret;
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u32 mask_val = 1 << wdt->drv_data->mask_bit;
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u32 val = 0;
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/* No need to do anything if no PMU CONFIG needed */
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if (!(wdt->drv_data->quirks & QUIRK_HAS_PMU_CONFIG))
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return 0;
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if (mask)
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val = mask_val;
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ret = regmap_update_bits(wdt->pmureg,
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wdt->drv_data->disable_reg,
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mask_val, val);
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if (ret < 0)
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goto error;
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ret = regmap_update_bits(wdt->pmureg,
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wdt->drv_data->mask_reset_reg,
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mask_val, val);
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error:
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if (ret < 0)
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dev_err(wdt->dev, "failed to update reg(%d)\n", ret);
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return ret;
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}
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static int s3c2410wdt_keepalive(struct watchdog_device *wdd)
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{
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struct s3c2410_wdt *wdt = watchdog_get_drvdata(wdd);
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spin_lock(&wdt->lock);
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writel(wdt->count, wdt->reg_base + S3C2410_WTCNT);
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spin_unlock(&wdt->lock);
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return 0;
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}
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static void __s3c2410wdt_stop(struct s3c2410_wdt *wdt)
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{
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unsigned long wtcon;
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wtcon = readl(wdt->reg_base + S3C2410_WTCON);
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wtcon &= ~(S3C2410_WTCON_ENABLE | S3C2410_WTCON_RSTEN);
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writel(wtcon, wdt->reg_base + S3C2410_WTCON);
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}
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static int s3c2410wdt_stop(struct watchdog_device *wdd)
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{
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struct s3c2410_wdt *wdt = watchdog_get_drvdata(wdd);
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spin_lock(&wdt->lock);
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__s3c2410wdt_stop(wdt);
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spin_unlock(&wdt->lock);
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return 0;
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}
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static int s3c2410wdt_start(struct watchdog_device *wdd)
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{
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unsigned long wtcon;
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struct s3c2410_wdt *wdt = watchdog_get_drvdata(wdd);
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spin_lock(&wdt->lock);
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__s3c2410wdt_stop(wdt);
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wtcon = readl(wdt->reg_base + S3C2410_WTCON);
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wtcon |= S3C2410_WTCON_ENABLE | S3C2410_WTCON_DIV128;
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if (soft_noboot) {
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wtcon |= S3C2410_WTCON_INTEN;
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wtcon &= ~S3C2410_WTCON_RSTEN;
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} else {
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wtcon &= ~S3C2410_WTCON_INTEN;
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wtcon |= S3C2410_WTCON_RSTEN;
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}
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DBG("%s: count=0x%08x, wtcon=%08lx\n",
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__func__, wdt->count, wtcon);
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writel(wdt->count, wdt->reg_base + S3C2410_WTDAT);
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writel(wdt->count, wdt->reg_base + S3C2410_WTCNT);
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writel(wtcon, wdt->reg_base + S3C2410_WTCON);
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spin_unlock(&wdt->lock);
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return 0;
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}
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static inline int s3c2410wdt_is_running(struct s3c2410_wdt *wdt)
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{
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return readl(wdt->reg_base + S3C2410_WTCON) & S3C2410_WTCON_ENABLE;
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}
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static int s3c2410wdt_set_heartbeat(struct watchdog_device *wdd, unsigned timeout)
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{
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struct s3c2410_wdt *wdt = watchdog_get_drvdata(wdd);
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unsigned long freq = clk_get_rate(wdt->clock);
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unsigned int count;
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unsigned int divisor = 1;
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unsigned long wtcon;
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if (timeout < 1)
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return -EINVAL;
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freq = DIV_ROUND_UP(freq, 128);
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count = timeout * freq;
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DBG("%s: count=%d, timeout=%d, freq=%lu\n",
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__func__, count, timeout, freq);
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/* if the count is bigger than the watchdog register,
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then work out what we need to do (and if) we can
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actually make this value
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*/
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if (count >= 0x10000) {
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divisor = DIV_ROUND_UP(count, 0xffff);
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if (divisor > 0x100) {
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dev_err(wdt->dev, "timeout %d too big\n", timeout);
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return -EINVAL;
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}
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}
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DBG("%s: timeout=%d, divisor=%d, count=%d (%08x)\n",
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__func__, timeout, divisor, count, DIV_ROUND_UP(count, divisor));
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count = DIV_ROUND_UP(count, divisor);
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wdt->count = count;
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/* update the pre-scaler */
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wtcon = readl(wdt->reg_base + S3C2410_WTCON);
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wtcon &= ~S3C2410_WTCON_PRESCALE_MASK;
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wtcon |= S3C2410_WTCON_PRESCALE(divisor-1);
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writel(count, wdt->reg_base + S3C2410_WTDAT);
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writel(wtcon, wdt->reg_base + S3C2410_WTCON);
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wdd->timeout = (count * divisor) / freq;
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return 0;
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}
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static int s3c2410wdt_restart(struct watchdog_device *wdd, unsigned long action,
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void *data)
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{
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struct s3c2410_wdt *wdt = watchdog_get_drvdata(wdd);
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void __iomem *wdt_base = wdt->reg_base;
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/* disable watchdog, to be safe */
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writel(0, wdt_base + S3C2410_WTCON);
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/* put initial values into count and data */
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writel(0x80, wdt_base + S3C2410_WTCNT);
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writel(0x80, wdt_base + S3C2410_WTDAT);
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/* set the watchdog to go and reset... */
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writel(S3C2410_WTCON_ENABLE | S3C2410_WTCON_DIV16 |
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S3C2410_WTCON_RSTEN | S3C2410_WTCON_PRESCALE(0x20),
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wdt_base + S3C2410_WTCON);
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/* wait for reset to assert... */
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mdelay(500);
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return 0;
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}
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#define OPTIONS (WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING | WDIOF_MAGICCLOSE)
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static const struct watchdog_info s3c2410_wdt_ident = {
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.options = OPTIONS,
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.firmware_version = 0,
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.identity = "S3C2410 Watchdog",
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};
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static struct watchdog_ops s3c2410wdt_ops = {
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.owner = THIS_MODULE,
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.start = s3c2410wdt_start,
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.stop = s3c2410wdt_stop,
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.ping = s3c2410wdt_keepalive,
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.set_timeout = s3c2410wdt_set_heartbeat,
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.restart = s3c2410wdt_restart,
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};
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static struct watchdog_device s3c2410_wdd = {
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.info = &s3c2410_wdt_ident,
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.ops = &s3c2410wdt_ops,
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.timeout = CONFIG_S3C2410_WATCHDOG_DEFAULT_TIME,
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};
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/* interrupt handler code */
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static irqreturn_t s3c2410wdt_irq(int irqno, void *param)
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{
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struct s3c2410_wdt *wdt = platform_get_drvdata(param);
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dev_info(wdt->dev, "watchdog timer expired (irq)\n");
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s3c2410wdt_keepalive(&wdt->wdt_device);
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return IRQ_HANDLED;
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}
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#ifdef CONFIG_ARM_S3C24XX_CPUFREQ
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static int s3c2410wdt_cpufreq_transition(struct notifier_block *nb,
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unsigned long val, void *data)
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{
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int ret;
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struct s3c2410_wdt *wdt = freq_to_wdt(nb);
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if (!s3c2410wdt_is_running(wdt))
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goto done;
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if (val == CPUFREQ_PRECHANGE) {
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/* To ensure that over the change we don't cause the
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* watchdog to trigger, we perform an keep-alive if
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* the watchdog is running.
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*/
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s3c2410wdt_keepalive(&wdt->wdt_device);
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|
} else if (val == CPUFREQ_POSTCHANGE) {
|
|
s3c2410wdt_stop(&wdt->wdt_device);
|
|
|
|
ret = s3c2410wdt_set_heartbeat(&wdt->wdt_device,
|
|
wdt->wdt_device.timeout);
|
|
|
|
if (ret >= 0)
|
|
s3c2410wdt_start(&wdt->wdt_device);
|
|
else
|
|
goto err;
|
|
}
|
|
|
|
done:
|
|
return 0;
|
|
|
|
err:
|
|
dev_err(wdt->dev, "cannot set new value for timeout %d\n",
|
|
wdt->wdt_device.timeout);
|
|
return ret;
|
|
}
|
|
|
|
static inline int s3c2410wdt_cpufreq_register(struct s3c2410_wdt *wdt)
|
|
{
|
|
wdt->freq_transition.notifier_call = s3c2410wdt_cpufreq_transition;
|
|
|
|
return cpufreq_register_notifier(&wdt->freq_transition,
|
|
CPUFREQ_TRANSITION_NOTIFIER);
|
|
}
|
|
|
|
static inline void s3c2410wdt_cpufreq_deregister(struct s3c2410_wdt *wdt)
|
|
{
|
|
wdt->freq_transition.notifier_call = s3c2410wdt_cpufreq_transition;
|
|
|
|
cpufreq_unregister_notifier(&wdt->freq_transition,
|
|
CPUFREQ_TRANSITION_NOTIFIER);
|
|
}
|
|
|
|
#else
|
|
|
|
static inline int s3c2410wdt_cpufreq_register(struct s3c2410_wdt *wdt)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
static inline void s3c2410wdt_cpufreq_deregister(struct s3c2410_wdt *wdt)
|
|
{
|
|
}
|
|
#endif
|
|
|
|
static inline unsigned int s3c2410wdt_get_bootstatus(struct s3c2410_wdt *wdt)
|
|
{
|
|
unsigned int rst_stat;
|
|
int ret;
|
|
|
|
if (!(wdt->drv_data->quirks & QUIRK_HAS_RST_STAT))
|
|
return 0;
|
|
|
|
ret = regmap_read(wdt->pmureg, wdt->drv_data->rst_stat_reg, &rst_stat);
|
|
if (ret)
|
|
dev_warn(wdt->dev, "Couldn't get RST_STAT register\n");
|
|
else if (rst_stat & BIT(wdt->drv_data->rst_stat_bit))
|
|
return WDIOF_CARDRESET;
|
|
|
|
return 0;
|
|
}
|
|
|
|
/* s3c2410_get_wdt_driver_data */
|
|
static inline struct s3c2410_wdt_variant *
|
|
get_wdt_drv_data(struct platform_device *pdev)
|
|
{
|
|
if (pdev->dev.of_node) {
|
|
const struct of_device_id *match;
|
|
match = of_match_node(s3c2410_wdt_match, pdev->dev.of_node);
|
|
return (struct s3c2410_wdt_variant *)match->data;
|
|
} else {
|
|
return (struct s3c2410_wdt_variant *)
|
|
platform_get_device_id(pdev)->driver_data;
|
|
}
|
|
}
|
|
|
|
static int s3c2410wdt_probe(struct platform_device *pdev)
|
|
{
|
|
struct device *dev;
|
|
struct s3c2410_wdt *wdt;
|
|
struct resource *wdt_mem;
|
|
struct resource *wdt_irq;
|
|
unsigned int wtcon;
|
|
int started = 0;
|
|
int ret;
|
|
|
|
DBG("%s: probe=%p\n", __func__, pdev);
|
|
|
|
dev = &pdev->dev;
|
|
|
|
wdt = devm_kzalloc(dev, sizeof(*wdt), GFP_KERNEL);
|
|
if (!wdt)
|
|
return -ENOMEM;
|
|
|
|
wdt->dev = &pdev->dev;
|
|
spin_lock_init(&wdt->lock);
|
|
wdt->wdt_device = s3c2410_wdd;
|
|
|
|
wdt->drv_data = get_wdt_drv_data(pdev);
|
|
if (wdt->drv_data->quirks & QUIRKS_HAVE_PMUREG) {
|
|
wdt->pmureg = syscon_regmap_lookup_by_phandle(dev->of_node,
|
|
"samsung,syscon-phandle");
|
|
if (IS_ERR(wdt->pmureg)) {
|
|
dev_err(dev, "syscon regmap lookup failed.\n");
|
|
return PTR_ERR(wdt->pmureg);
|
|
}
|
|
}
|
|
|
|
wdt_irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
|
|
if (wdt_irq == NULL) {
|
|
dev_err(dev, "no irq resource specified\n");
|
|
ret = -ENOENT;
|
|
goto err;
|
|
}
|
|
|
|
/* get the memory region for the watchdog timer */
|
|
wdt_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
wdt->reg_base = devm_ioremap_resource(dev, wdt_mem);
|
|
if (IS_ERR(wdt->reg_base)) {
|
|
ret = PTR_ERR(wdt->reg_base);
|
|
goto err;
|
|
}
|
|
|
|
DBG("probe: mapped reg_base=%p\n", wdt->reg_base);
|
|
|
|
wdt->clock = devm_clk_get(dev, "watchdog");
|
|
if (IS_ERR(wdt->clock)) {
|
|
dev_err(dev, "failed to find watchdog clock source\n");
|
|
ret = PTR_ERR(wdt->clock);
|
|
goto err;
|
|
}
|
|
|
|
ret = clk_prepare_enable(wdt->clock);
|
|
if (ret < 0) {
|
|
dev_err(dev, "failed to enable clock\n");
|
|
return ret;
|
|
}
|
|
|
|
wdt->wdt_device.min_timeout = 1;
|
|
wdt->wdt_device.max_timeout = s3c2410wdt_max_timeout(wdt->clock);
|
|
|
|
ret = s3c2410wdt_cpufreq_register(wdt);
|
|
if (ret < 0) {
|
|
dev_err(dev, "failed to register cpufreq\n");
|
|
goto err_clk;
|
|
}
|
|
|
|
watchdog_set_drvdata(&wdt->wdt_device, wdt);
|
|
|
|
/* see if we can actually set the requested timer margin, and if
|
|
* not, try the default value */
|
|
|
|
watchdog_init_timeout(&wdt->wdt_device, tmr_margin, &pdev->dev);
|
|
ret = s3c2410wdt_set_heartbeat(&wdt->wdt_device,
|
|
wdt->wdt_device.timeout);
|
|
if (ret) {
|
|
started = s3c2410wdt_set_heartbeat(&wdt->wdt_device,
|
|
CONFIG_S3C2410_WATCHDOG_DEFAULT_TIME);
|
|
|
|
if (started == 0)
|
|
dev_info(dev,
|
|
"tmr_margin value out of range, default %d used\n",
|
|
CONFIG_S3C2410_WATCHDOG_DEFAULT_TIME);
|
|
else
|
|
dev_info(dev, "default timer value is out of range, "
|
|
"cannot start\n");
|
|
}
|
|
|
|
ret = devm_request_irq(dev, wdt_irq->start, s3c2410wdt_irq, 0,
|
|
pdev->name, pdev);
|
|
if (ret != 0) {
|
|
dev_err(dev, "failed to install irq (%d)\n", ret);
|
|
goto err_cpufreq;
|
|
}
|
|
|
|
watchdog_set_nowayout(&wdt->wdt_device, nowayout);
|
|
watchdog_set_restart_priority(&wdt->wdt_device, 128);
|
|
|
|
wdt->wdt_device.bootstatus = s3c2410wdt_get_bootstatus(wdt);
|
|
wdt->wdt_device.parent = &pdev->dev;
|
|
|
|
ret = watchdog_register_device(&wdt->wdt_device);
|
|
if (ret) {
|
|
dev_err(dev, "cannot register watchdog (%d)\n", ret);
|
|
goto err_cpufreq;
|
|
}
|
|
|
|
ret = s3c2410wdt_mask_and_disable_reset(wdt, false);
|
|
if (ret < 0)
|
|
goto err_unregister;
|
|
|
|
if (tmr_atboot && started == 0) {
|
|
dev_info(dev, "starting watchdog timer\n");
|
|
s3c2410wdt_start(&wdt->wdt_device);
|
|
} else if (!tmr_atboot) {
|
|
/* if we're not enabling the watchdog, then ensure it is
|
|
* disabled if it has been left running from the bootloader
|
|
* or other source */
|
|
|
|
s3c2410wdt_stop(&wdt->wdt_device);
|
|
}
|
|
|
|
platform_set_drvdata(pdev, wdt);
|
|
|
|
/* print out a statement of readiness */
|
|
|
|
wtcon = readl(wdt->reg_base + S3C2410_WTCON);
|
|
|
|
dev_info(dev, "watchdog %sactive, reset %sabled, irq %sabled\n",
|
|
(wtcon & S3C2410_WTCON_ENABLE) ? "" : "in",
|
|
(wtcon & S3C2410_WTCON_RSTEN) ? "en" : "dis",
|
|
(wtcon & S3C2410_WTCON_INTEN) ? "en" : "dis");
|
|
|
|
return 0;
|
|
|
|
err_unregister:
|
|
watchdog_unregister_device(&wdt->wdt_device);
|
|
|
|
err_cpufreq:
|
|
s3c2410wdt_cpufreq_deregister(wdt);
|
|
|
|
err_clk:
|
|
clk_disable_unprepare(wdt->clock);
|
|
|
|
err:
|
|
return ret;
|
|
}
|
|
|
|
static int s3c2410wdt_remove(struct platform_device *dev)
|
|
{
|
|
int ret;
|
|
struct s3c2410_wdt *wdt = platform_get_drvdata(dev);
|
|
|
|
ret = s3c2410wdt_mask_and_disable_reset(wdt, true);
|
|
if (ret < 0)
|
|
return ret;
|
|
|
|
watchdog_unregister_device(&wdt->wdt_device);
|
|
|
|
s3c2410wdt_cpufreq_deregister(wdt);
|
|
|
|
clk_disable_unprepare(wdt->clock);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void s3c2410wdt_shutdown(struct platform_device *dev)
|
|
{
|
|
struct s3c2410_wdt *wdt = platform_get_drvdata(dev);
|
|
|
|
s3c2410wdt_mask_and_disable_reset(wdt, true);
|
|
|
|
s3c2410wdt_stop(&wdt->wdt_device);
|
|
}
|
|
|
|
#ifdef CONFIG_PM_SLEEP
|
|
|
|
static int s3c2410wdt_suspend(struct device *dev)
|
|
{
|
|
int ret;
|
|
struct s3c2410_wdt *wdt = dev_get_drvdata(dev);
|
|
|
|
/* Save watchdog state, and turn it off. */
|
|
wdt->wtcon_save = readl(wdt->reg_base + S3C2410_WTCON);
|
|
wdt->wtdat_save = readl(wdt->reg_base + S3C2410_WTDAT);
|
|
|
|
ret = s3c2410wdt_mask_and_disable_reset(wdt, true);
|
|
if (ret < 0)
|
|
return ret;
|
|
|
|
/* Note that WTCNT doesn't need to be saved. */
|
|
s3c2410wdt_stop(&wdt->wdt_device);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int s3c2410wdt_resume(struct device *dev)
|
|
{
|
|
int ret;
|
|
struct s3c2410_wdt *wdt = dev_get_drvdata(dev);
|
|
|
|
/* Restore watchdog state. */
|
|
writel(wdt->wtdat_save, wdt->reg_base + S3C2410_WTDAT);
|
|
writel(wdt->wtdat_save, wdt->reg_base + S3C2410_WTCNT);/* Reset count */
|
|
writel(wdt->wtcon_save, wdt->reg_base + S3C2410_WTCON);
|
|
|
|
ret = s3c2410wdt_mask_and_disable_reset(wdt, false);
|
|
if (ret < 0)
|
|
return ret;
|
|
|
|
dev_info(dev, "watchdog %sabled\n",
|
|
(wdt->wtcon_save & S3C2410_WTCON_ENABLE) ? "en" : "dis");
|
|
|
|
return 0;
|
|
}
|
|
#endif
|
|
|
|
static SIMPLE_DEV_PM_OPS(s3c2410wdt_pm_ops, s3c2410wdt_suspend,
|
|
s3c2410wdt_resume);
|
|
|
|
static struct platform_driver s3c2410wdt_driver = {
|
|
.probe = s3c2410wdt_probe,
|
|
.remove = s3c2410wdt_remove,
|
|
.shutdown = s3c2410wdt_shutdown,
|
|
.id_table = s3c2410_wdt_ids,
|
|
.driver = {
|
|
.name = "s3c2410-wdt",
|
|
.pm = &s3c2410wdt_pm_ops,
|
|
.of_match_table = of_match_ptr(s3c2410_wdt_match),
|
|
},
|
|
};
|
|
|
|
module_platform_driver(s3c2410wdt_driver);
|
|
|
|
MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>, "
|
|
"Dimitry Andric <dimitry.andric@tomtom.com>");
|
|
MODULE_DESCRIPTION("S3C2410 Watchdog Device Driver");
|
|
MODULE_LICENSE("GPL");
|