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0370964dd3
On a VHE system, the EL1 state is left in the CPU most of the time, and only syncronized back to memory when vcpu_put() is called (most of the time on preemption). Which means that when injecting an exception, we'd better have a way to either: (1) write directly to the EL1 sysregs (2) synchronize the state back to memory, and do the changes there For an AArch64, we already do (1), so we are safe. Unfortunately, doing the same thing for AArch32 would be pretty invasive. Instead, we can easily implement (2) by calling the put/load architectural backends, and keep preemption disabled. We can then reload the state back into EL1. Cc: stable@vger.kernel.org Reported-by: James Morse <james.morse@arm.com> Signed-off-by: Marc Zyngier <maz@kernel.org>
232 lines
6.1 KiB
C
232 lines
6.1 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* (not much of an) Emulation layer for 32bit guests.
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*
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* Copyright (C) 2012,2013 - ARM Ltd
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* Author: Marc Zyngier <marc.zyngier@arm.com>
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*
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* based on arch/arm/kvm/emulate.c
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* Copyright (C) 2012 - Virtual Open Systems and Columbia University
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* Author: Christoffer Dall <c.dall@virtualopensystems.com>
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*/
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#include <linux/bits.h>
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#include <linux/kvm_host.h>
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#include <asm/kvm_emulate.h>
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#include <asm/kvm_hyp.h>
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#define DFSR_FSC_EXTABT_LPAE 0x10
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#define DFSR_FSC_EXTABT_nLPAE 0x08
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#define DFSR_LPAE BIT(9)
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/*
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* Table taken from ARMv8 ARM DDI0487B-B, table G1-10.
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*/
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static const u8 return_offsets[8][2] = {
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[0] = { 0, 0 }, /* Reset, unused */
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[1] = { 4, 2 }, /* Undefined */
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[2] = { 0, 0 }, /* SVC, unused */
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[3] = { 4, 4 }, /* Prefetch abort */
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[4] = { 8, 8 }, /* Data abort */
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[5] = { 0, 0 }, /* HVC, unused */
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[6] = { 4, 4 }, /* IRQ, unused */
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[7] = { 4, 4 }, /* FIQ, unused */
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};
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static bool pre_fault_synchronize(struct kvm_vcpu *vcpu)
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{
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preempt_disable();
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if (vcpu->arch.sysregs_loaded_on_cpu) {
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kvm_arch_vcpu_put(vcpu);
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return true;
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}
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preempt_enable();
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return false;
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}
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static void post_fault_synchronize(struct kvm_vcpu *vcpu, bool loaded)
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{
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if (loaded) {
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kvm_arch_vcpu_load(vcpu, smp_processor_id());
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preempt_enable();
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}
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}
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/*
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* When an exception is taken, most CPSR fields are left unchanged in the
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* handler. However, some are explicitly overridden (e.g. M[4:0]).
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*
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* The SPSR/SPSR_ELx layouts differ, and the below is intended to work with
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* either format. Note: SPSR.J bit doesn't exist in SPSR_ELx, but this bit was
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* obsoleted by the ARMv7 virtualization extensions and is RES0.
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*
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* For the SPSR layout seen from AArch32, see:
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* - ARM DDI 0406C.d, page B1-1148
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* - ARM DDI 0487E.a, page G8-6264
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*
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* For the SPSR_ELx layout for AArch32 seen from AArch64, see:
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* - ARM DDI 0487E.a, page C5-426
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*
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* Here we manipulate the fields in order of the AArch32 SPSR_ELx layout, from
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* MSB to LSB.
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*/
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static unsigned long get_except32_cpsr(struct kvm_vcpu *vcpu, u32 mode)
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{
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u32 sctlr = vcpu_cp15(vcpu, c1_SCTLR);
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unsigned long old, new;
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old = *vcpu_cpsr(vcpu);
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new = 0;
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new |= (old & PSR_AA32_N_BIT);
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new |= (old & PSR_AA32_Z_BIT);
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new |= (old & PSR_AA32_C_BIT);
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new |= (old & PSR_AA32_V_BIT);
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new |= (old & PSR_AA32_Q_BIT);
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// CPSR.IT[7:0] are set to zero upon any exception
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// See ARM DDI 0487E.a, section G1.12.3
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// See ARM DDI 0406C.d, section B1.8.3
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new |= (old & PSR_AA32_DIT_BIT);
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// CPSR.SSBS is set to SCTLR.DSSBS upon any exception
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// See ARM DDI 0487E.a, page G8-6244
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if (sctlr & BIT(31))
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new |= PSR_AA32_SSBS_BIT;
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// CPSR.PAN is unchanged unless SCTLR.SPAN == 0b0
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// SCTLR.SPAN is RES1 when ARMv8.1-PAN is not implemented
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// See ARM DDI 0487E.a, page G8-6246
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new |= (old & PSR_AA32_PAN_BIT);
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if (!(sctlr & BIT(23)))
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new |= PSR_AA32_PAN_BIT;
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// SS does not exist in AArch32, so ignore
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// CPSR.IL is set to zero upon any exception
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// See ARM DDI 0487E.a, page G1-5527
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new |= (old & PSR_AA32_GE_MASK);
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// CPSR.IT[7:0] are set to zero upon any exception
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// See prior comment above
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// CPSR.E is set to SCTLR.EE upon any exception
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// See ARM DDI 0487E.a, page G8-6245
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// See ARM DDI 0406C.d, page B4-1701
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if (sctlr & BIT(25))
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new |= PSR_AA32_E_BIT;
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// CPSR.A is unchanged upon an exception to Undefined, Supervisor
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// CPSR.A is set upon an exception to other modes
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// See ARM DDI 0487E.a, pages G1-5515 to G1-5516
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// See ARM DDI 0406C.d, page B1-1182
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new |= (old & PSR_AA32_A_BIT);
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if (mode != PSR_AA32_MODE_UND && mode != PSR_AA32_MODE_SVC)
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new |= PSR_AA32_A_BIT;
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// CPSR.I is set upon any exception
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// See ARM DDI 0487E.a, pages G1-5515 to G1-5516
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// See ARM DDI 0406C.d, page B1-1182
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new |= PSR_AA32_I_BIT;
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// CPSR.F is set upon an exception to FIQ
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// CPSR.F is unchanged upon an exception to other modes
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// See ARM DDI 0487E.a, pages G1-5515 to G1-5516
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// See ARM DDI 0406C.d, page B1-1182
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new |= (old & PSR_AA32_F_BIT);
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if (mode == PSR_AA32_MODE_FIQ)
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new |= PSR_AA32_F_BIT;
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// CPSR.T is set to SCTLR.TE upon any exception
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// See ARM DDI 0487E.a, page G8-5514
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// See ARM DDI 0406C.d, page B1-1181
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if (sctlr & BIT(30))
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new |= PSR_AA32_T_BIT;
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new |= mode;
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return new;
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}
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static void prepare_fault32(struct kvm_vcpu *vcpu, u32 mode, u32 vect_offset)
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{
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unsigned long spsr = *vcpu_cpsr(vcpu);
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bool is_thumb = (spsr & PSR_AA32_T_BIT);
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u32 return_offset = return_offsets[vect_offset >> 2][is_thumb];
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u32 sctlr = vcpu_cp15(vcpu, c1_SCTLR);
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*vcpu_cpsr(vcpu) = get_except32_cpsr(vcpu, mode);
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/* Note: These now point to the banked copies */
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vcpu_write_spsr(vcpu, host_spsr_to_spsr32(spsr));
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*vcpu_reg32(vcpu, 14) = *vcpu_pc(vcpu) + return_offset;
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/* Branch to exception vector */
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if (sctlr & (1 << 13))
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vect_offset += 0xffff0000;
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else /* always have security exceptions */
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vect_offset += vcpu_cp15(vcpu, c12_VBAR);
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*vcpu_pc(vcpu) = vect_offset;
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}
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void kvm_inject_undef32(struct kvm_vcpu *vcpu)
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{
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bool loaded = pre_fault_synchronize(vcpu);
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prepare_fault32(vcpu, PSR_AA32_MODE_UND, 4);
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post_fault_synchronize(vcpu, loaded);
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}
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/*
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* Modelled after TakeDataAbortException() and TakePrefetchAbortException
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* pseudocode.
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*/
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static void inject_abt32(struct kvm_vcpu *vcpu, bool is_pabt,
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unsigned long addr)
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{
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u32 vect_offset;
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u32 *far, *fsr;
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bool is_lpae;
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bool loaded;
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loaded = pre_fault_synchronize(vcpu);
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if (is_pabt) {
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vect_offset = 12;
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far = &vcpu_cp15(vcpu, c6_IFAR);
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fsr = &vcpu_cp15(vcpu, c5_IFSR);
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} else { /* !iabt */
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vect_offset = 16;
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far = &vcpu_cp15(vcpu, c6_DFAR);
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fsr = &vcpu_cp15(vcpu, c5_DFSR);
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}
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prepare_fault32(vcpu, PSR_AA32_MODE_ABT, vect_offset);
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*far = addr;
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/* Give the guest an IMPLEMENTATION DEFINED exception */
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is_lpae = (vcpu_cp15(vcpu, c2_TTBCR) >> 31);
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if (is_lpae) {
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*fsr = DFSR_LPAE | DFSR_FSC_EXTABT_LPAE;
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} else {
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/* no need to shuffle FS[4] into DFSR[10] as its 0 */
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*fsr = DFSR_FSC_EXTABT_nLPAE;
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}
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post_fault_synchronize(vcpu, loaded);
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}
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void kvm_inject_dabt32(struct kvm_vcpu *vcpu, unsigned long addr)
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{
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inject_abt32(vcpu, false, addr);
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}
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void kvm_inject_pabt32(struct kvm_vcpu *vcpu, unsigned long addr)
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{
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inject_abt32(vcpu, true, addr);
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}
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