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![Dan Carpenter](/assets/img/avatar_default.png)
Currently, when irq_domain_add_linear() fails, the error code does not get
set so it returns zero which is wrong. Fix it by setting the appropriate
error code.
Fixes: 9e543e22e2
("irqchip: Add driver for Loongson-1 interrupt controller")
Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Reviewed-by: Mukesh Ojha <mojha@codeaurora.org>
Cc: Marc Zyngier <marc.zyngier@arm.com>
Cc: Jiaxun Yang <jiaxun.yang@flygoat.com>
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: kernel-janitors@vger.kernel.org
Link: https://lkml.kernel.org/r/20190329062136.GQ32613@kadam
193 lines
4.7 KiB
C
193 lines
4.7 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2019, Jiaxun Yang <jiaxun.yang@flygoat.com>
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* Loongson-1 platform IRQ support
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*/
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#include <linux/errno.h>
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#include <linux/init.h>
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#include <linux/types.h>
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#include <linux/interrupt.h>
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#include <linux/ioport.h>
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#include <linux/irqchip.h>
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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#include <linux/io.h>
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#include <linux/irqchip/chained_irq.h>
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#define LS_REG_INTC_STATUS 0x00
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#define LS_REG_INTC_EN 0x04
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#define LS_REG_INTC_SET 0x08
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#define LS_REG_INTC_CLR 0x0c
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#define LS_REG_INTC_POL 0x10
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#define LS_REG_INTC_EDGE 0x14
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/**
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* struct ls1x_intc_priv - private ls1x-intc data.
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* @domain: IRQ domain.
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* @intc_base: IO Base of intc registers.
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*/
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struct ls1x_intc_priv {
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struct irq_domain *domain;
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void __iomem *intc_base;
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};
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static void ls1x_chained_handle_irq(struct irq_desc *desc)
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{
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struct ls1x_intc_priv *priv = irq_desc_get_handler_data(desc);
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struct irq_chip *chip = irq_desc_get_chip(desc);
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u32 pending;
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chained_irq_enter(chip, desc);
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pending = readl(priv->intc_base + LS_REG_INTC_STATUS) &
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readl(priv->intc_base + LS_REG_INTC_EN);
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if (!pending)
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spurious_interrupt();
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while (pending) {
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int bit = __ffs(pending);
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generic_handle_irq(irq_find_mapping(priv->domain, bit));
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pending &= ~BIT(bit);
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}
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chained_irq_exit(chip, desc);
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}
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static void ls_intc_set_bit(struct irq_chip_generic *gc,
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unsigned int offset,
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u32 mask, bool set)
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{
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if (set)
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writel(readl(gc->reg_base + offset) | mask,
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gc->reg_base + offset);
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else
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writel(readl(gc->reg_base + offset) & ~mask,
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gc->reg_base + offset);
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}
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static int ls_intc_set_type(struct irq_data *data, unsigned int type)
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{
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struct irq_chip_generic *gc = irq_data_get_irq_chip_data(data);
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u32 mask = data->mask;
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switch (type) {
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case IRQ_TYPE_LEVEL_HIGH:
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ls_intc_set_bit(gc, LS_REG_INTC_EDGE, mask, false);
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ls_intc_set_bit(gc, LS_REG_INTC_POL, mask, true);
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break;
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case IRQ_TYPE_LEVEL_LOW:
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ls_intc_set_bit(gc, LS_REG_INTC_EDGE, mask, false);
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ls_intc_set_bit(gc, LS_REG_INTC_POL, mask, false);
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break;
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case IRQ_TYPE_EDGE_RISING:
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ls_intc_set_bit(gc, LS_REG_INTC_EDGE, mask, true);
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ls_intc_set_bit(gc, LS_REG_INTC_POL, mask, true);
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break;
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case IRQ_TYPE_EDGE_FALLING:
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ls_intc_set_bit(gc, LS_REG_INTC_EDGE, mask, true);
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ls_intc_set_bit(gc, LS_REG_INTC_POL, mask, false);
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break;
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default:
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return -EINVAL;
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}
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irqd_set_trigger_type(data, type);
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return irq_setup_alt_chip(data, type);
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}
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static int __init ls1x_intc_of_init(struct device_node *node,
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struct device_node *parent)
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{
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struct irq_chip_generic *gc;
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struct irq_chip_type *ct;
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struct ls1x_intc_priv *priv;
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int parent_irq, err = 0;
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priv = kzalloc(sizeof(*priv), GFP_KERNEL);
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if (!priv)
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return -ENOMEM;
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priv->intc_base = of_iomap(node, 0);
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if (!priv->intc_base) {
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err = -ENODEV;
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goto out_free_priv;
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}
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parent_irq = irq_of_parse_and_map(node, 0);
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if (!parent_irq) {
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pr_err("ls1x-irq: unable to get parent irq\n");
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err = -ENODEV;
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goto out_iounmap;
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}
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/* Set up an IRQ domain */
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priv->domain = irq_domain_add_linear(node, 32, &irq_generic_chip_ops,
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NULL);
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if (!priv->domain) {
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pr_err("ls1x-irq: cannot add IRQ domain\n");
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err = -ENOMEM;
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goto out_iounmap;
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}
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err = irq_alloc_domain_generic_chips(priv->domain, 32, 2,
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node->full_name, handle_level_irq,
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IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN, 0,
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IRQ_GC_INIT_MASK_CACHE);
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if (err) {
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pr_err("ls1x-irq: unable to register IRQ domain\n");
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goto out_free_domain;
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}
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/* Mask all irqs */
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writel(0x0, priv->intc_base + LS_REG_INTC_EN);
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/* Ack all irqs */
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writel(0xffffffff, priv->intc_base + LS_REG_INTC_CLR);
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/* Set all irqs to high level triggered */
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writel(0xffffffff, priv->intc_base + LS_REG_INTC_POL);
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gc = irq_get_domain_generic_chip(priv->domain, 0);
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gc->reg_base = priv->intc_base;
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ct = gc->chip_types;
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ct[0].type = IRQ_TYPE_LEVEL_MASK;
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ct[0].regs.mask = LS_REG_INTC_EN;
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ct[0].regs.ack = LS_REG_INTC_CLR;
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ct[0].chip.irq_unmask = irq_gc_mask_set_bit;
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ct[0].chip.irq_mask = irq_gc_mask_clr_bit;
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ct[0].chip.irq_ack = irq_gc_ack_set_bit;
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ct[0].chip.irq_set_type = ls_intc_set_type;
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ct[0].handler = handle_level_irq;
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ct[1].type = IRQ_TYPE_EDGE_BOTH;
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ct[1].regs.mask = LS_REG_INTC_EN;
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ct[1].regs.ack = LS_REG_INTC_CLR;
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ct[1].chip.irq_unmask = irq_gc_mask_set_bit;
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ct[1].chip.irq_mask = irq_gc_mask_clr_bit;
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ct[1].chip.irq_ack = irq_gc_ack_set_bit;
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ct[1].chip.irq_set_type = ls_intc_set_type;
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ct[1].handler = handle_edge_irq;
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irq_set_chained_handler_and_data(parent_irq,
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ls1x_chained_handle_irq, priv);
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return 0;
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out_free_domain:
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irq_domain_remove(priv->domain);
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out_iounmap:
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iounmap(priv->intc_base);
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out_free_priv:
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kfree(priv);
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return err;
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}
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IRQCHIP_DECLARE(ls1x_intc, "loongson,ls1x-intc", ls1x_intc_of_init);
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