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https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2024-08-26 10:49:33 +00:00
![Linus Torvalds](/assets/img/avatar_default.png)
Including: - ARM SMMU and Mediatek updates from Will Deacon: - Support for MT8192 IOMMU from Mediatek - Arm v7s io-pgtable extensions for MT8192 - Removal of TLBI_ON_MAP quirk - New Qualcomm compatible strings - Allow SVA without hardware broadcast TLB maintenance on SMMUv3 - Virtualization Host Extension support for SMMUv3 (SVA) - Allow SMMUv3 PMU (perf) driver to be built independently from IOMMU - Some tidy-up in IOVA and core code - Conversion of the AMD IOMMU code to use the generic IO-page-table framework - Intel VT-d updates from Lu Baolu: - Audit capability consistency among different IOMMUs - Add SATC reporting structure support - Add iotlb_sync_map callback support - SDHI Support for Renesas IOMMU driver - Misc Cleanups and other small improvments -----BEGIN PGP SIGNATURE----- iQIzBAABCAAdFiEEr9jSbILcajRFYWYyK/BELZcBGuMFAmAz2AcACgkQK/BELZcB GuMflRAAyOfXzFqfmniYKxXmxAhOIlibCoojXzecItifdyaFkvUhxCadRg5u3dLH IeACDvUiaA5VQnVhjI0a7gCckKdq5YDwwAS+GQICUKNEZtWwrHwm2QTRBmL9MOlA v+iTrhYCqZWIAPe16BP5L4u6q4JWS2N9oNmDp6ia1VIhPjfsHU+gXpYKSxiLicmV VECAHJk5/JrwKXBP2nMg3ZqGz9RoJc2CzC4zvKu7ADDB9Zl+pXs74mb4ta81Y3G4 vf07G/ORYJjbMskz5KcmYw2897I9ejMrNaHrYNjlh2IDpGqmoCJ4+8vuVO0zslrm GzMOHMshaI653BmuRDHyczwNrNxMxSX3NOeR2fp76d3MSouK7RoFMr7ghMAegp1u qmSrqFbgnOT4cdzN8QpPyU22lmVHtQHm0P4EpZZzC95dtJo1nzt8BFrDjPdJDOyZ D7oKvZq+OA6MtjCN4gZ2ClxQoiUZ8E/jP1uGIknpzR1oeWnyEFtx8aI9q4yRjNcp n8UR7wFqbOIV0O/QC7UlEp/xSpG7BDN4BkvIgbH2qe6LmRmejCrnUWv6pkmPc9sI wFgV/Qnh9oo7yf6zvmCsi1r0kmfGLPRe8GB9+eN3wY3xxzDOLJEJNdVghWaP8Rz7 MBcL/0u8+fMfQlRiOPX64BSIF7fFPY0r0+erINawf1VUbyjUsUE= =xSX1 -----END PGP SIGNATURE----- Merge tag 'iommu-updates-v5.12' of git://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu Pull iommu updates from Joerg Roedel: - ARM SMMU and Mediatek updates from Will Deacon: - Support for MT8192 IOMMU from Mediatek - Arm v7s io-pgtable extensions for MT8192 - Removal of TLBI_ON_MAP quirk - New Qualcomm compatible strings - Allow SVA without hardware broadcast TLB maintenance on SMMUv3 - Virtualization Host Extension support for SMMUv3 (SVA) - Allow SMMUv3 PMU perf driver to be built independently from IOMMU - Some tidy-up in IOVA and core code - Conversion of the AMD IOMMU code to use the generic IO-page-table framework - Intel VT-d updates from Lu Baolu: - Audit capability consistency among different IOMMUs - Add SATC reporting structure support - Add iotlb_sync_map callback support - SDHI support for Renesas IOMMU driver - Misc cleanups and other small improvments * tag 'iommu-updates-v5.12' of git://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu: (94 commits) iommu/amd: Fix performance counter initialization MAINTAINERS: repair file pattern in MEDIATEK IOMMU DRIVER iommu/mediatek: Fix error code in probe() iommu/mediatek: Fix unsigned domid comparison with less than zero iommu/vt-d: Parse SATC reporting structure iommu/vt-d: Add new enum value and structure for SATC iommu/vt-d: Add iotlb_sync_map callback iommu/vt-d: Move capability check code to cap_audit files iommu/vt-d: Audit IOMMU Capabilities and add helper functions iommu/vt-d: Fix 'physical' typos iommu: Properly pass gfp_t in _iommu_map() to avoid atomic sleeping iommu/vt-d: Fix compile error [-Werror=implicit-function-declaration] driver/perf: Remove ARM_SMMU_V3_PMU dependency on ARM_SMMU_V3 MAINTAINERS: Add entry for MediaTek IOMMU iommu/mediatek: Add mt8192 support iommu/mediatek: Remove unnecessary check in attach_device iommu/mediatek: Support master use iova over 32bit iommu/mediatek: Add iova reserved function iommu/mediatek: Support for multi domains iommu/mediatek: Add get_domain_id from dev->dma_range_map ...
616 lines
16 KiB
C
616 lines
16 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) 2015-2016 MediaTek Inc.
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* Author: Yong Wu <yong.wu@mediatek.com>
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*/
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#include <linux/clk.h>
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#include <linux/component.h>
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#include <linux/device.h>
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#include <linux/err.h>
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#include <linux/io.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_platform.h>
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#include <linux/platform_device.h>
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#include <linux/pm_runtime.h>
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#include <soc/mediatek/smi.h>
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#include <dt-bindings/memory/mt2701-larb-port.h>
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#include <dt-bindings/memory/mtk-memory-port.h>
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/* mt8173 */
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#define SMI_LARB_MMU_EN 0xf00
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/* mt8167 */
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#define MT8167_SMI_LARB_MMU_EN 0xfc0
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/* mt2701 */
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#define REG_SMI_SECUR_CON_BASE 0x5c0
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/* every register control 8 port, register offset 0x4 */
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#define REG_SMI_SECUR_CON_OFFSET(id) (((id) >> 3) << 2)
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#define REG_SMI_SECUR_CON_ADDR(id) \
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(REG_SMI_SECUR_CON_BASE + REG_SMI_SECUR_CON_OFFSET(id))
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/*
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* every port have 4 bit to control, bit[port + 3] control virtual or physical,
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* bit[port + 2 : port + 1] control the domain, bit[port] control the security
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* or non-security.
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*/
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#define SMI_SECUR_CON_VAL_MSK(id) (~(0xf << (((id) & 0x7) << 2)))
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#define SMI_SECUR_CON_VAL_VIRT(id) BIT((((id) & 0x7) << 2) + 3)
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/* mt2701 domain should be set to 3 */
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#define SMI_SECUR_CON_VAL_DOMAIN(id) (0x3 << ((((id) & 0x7) << 2) + 1))
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/* mt2712 */
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#define SMI_LARB_NONSEC_CON(id) (0x380 + ((id) * 4))
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#define F_MMU_EN BIT(0)
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#define BANK_SEL(id) ({ \
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u32 _id = (id) & 0x3; \
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(_id << 8 | _id << 10 | _id << 12 | _id << 14); \
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})
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/* SMI COMMON */
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#define SMI_BUS_SEL 0x220
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#define SMI_BUS_LARB_SHIFT(larbid) ((larbid) << 1)
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/* All are MMU0 defaultly. Only specialize mmu1 here. */
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#define F_MMU1_LARB(larbid) (0x1 << SMI_BUS_LARB_SHIFT(larbid))
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enum mtk_smi_gen {
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MTK_SMI_GEN1,
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MTK_SMI_GEN2
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};
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struct mtk_smi_common_plat {
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enum mtk_smi_gen gen;
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bool has_gals;
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u32 bus_sel; /* Balance some larbs to enter mmu0 or mmu1 */
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};
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struct mtk_smi_larb_gen {
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int port_in_larb[MTK_LARB_NR_MAX + 1];
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void (*config_port)(struct device *dev);
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unsigned int larb_direct_to_common_mask;
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bool has_gals;
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};
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struct mtk_smi {
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struct device *dev;
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struct clk *clk_apb, *clk_smi;
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struct clk *clk_gals0, *clk_gals1;
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struct clk *clk_async; /*only needed by mt2701*/
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union {
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void __iomem *smi_ao_base; /* only for gen1 */
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void __iomem *base; /* only for gen2 */
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};
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const struct mtk_smi_common_plat *plat;
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};
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struct mtk_smi_larb { /* larb: local arbiter */
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struct mtk_smi smi;
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void __iomem *base;
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struct device *smi_common_dev;
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const struct mtk_smi_larb_gen *larb_gen;
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int larbid;
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u32 *mmu;
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unsigned char *bank;
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};
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static int mtk_smi_clk_enable(const struct mtk_smi *smi)
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{
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int ret;
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ret = clk_prepare_enable(smi->clk_apb);
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if (ret)
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return ret;
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ret = clk_prepare_enable(smi->clk_smi);
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if (ret)
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goto err_disable_apb;
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ret = clk_prepare_enable(smi->clk_gals0);
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if (ret)
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goto err_disable_smi;
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ret = clk_prepare_enable(smi->clk_gals1);
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if (ret)
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goto err_disable_gals0;
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return 0;
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err_disable_gals0:
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clk_disable_unprepare(smi->clk_gals0);
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err_disable_smi:
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clk_disable_unprepare(smi->clk_smi);
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err_disable_apb:
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clk_disable_unprepare(smi->clk_apb);
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return ret;
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}
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static void mtk_smi_clk_disable(const struct mtk_smi *smi)
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{
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clk_disable_unprepare(smi->clk_gals1);
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clk_disable_unprepare(smi->clk_gals0);
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clk_disable_unprepare(smi->clk_smi);
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clk_disable_unprepare(smi->clk_apb);
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}
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int mtk_smi_larb_get(struct device *larbdev)
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{
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int ret = pm_runtime_resume_and_get(larbdev);
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return (ret < 0) ? ret : 0;
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}
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EXPORT_SYMBOL_GPL(mtk_smi_larb_get);
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void mtk_smi_larb_put(struct device *larbdev)
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{
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pm_runtime_put_sync(larbdev);
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}
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EXPORT_SYMBOL_GPL(mtk_smi_larb_put);
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static int
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mtk_smi_larb_bind(struct device *dev, struct device *master, void *data)
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{
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struct mtk_smi_larb *larb = dev_get_drvdata(dev);
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struct mtk_smi_larb_iommu *larb_mmu = data;
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unsigned int i;
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for (i = 0; i < MTK_LARB_NR_MAX; i++) {
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if (dev == larb_mmu[i].dev) {
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larb->larbid = i;
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larb->mmu = &larb_mmu[i].mmu;
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larb->bank = larb_mmu[i].bank;
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return 0;
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}
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}
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return -ENODEV;
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}
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static void mtk_smi_larb_config_port_gen2_general(struct device *dev)
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{
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struct mtk_smi_larb *larb = dev_get_drvdata(dev);
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u32 reg;
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int i;
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if (BIT(larb->larbid) & larb->larb_gen->larb_direct_to_common_mask)
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return;
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for_each_set_bit(i, (unsigned long *)larb->mmu, 32) {
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reg = readl_relaxed(larb->base + SMI_LARB_NONSEC_CON(i));
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reg |= F_MMU_EN;
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reg |= BANK_SEL(larb->bank[i]);
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writel(reg, larb->base + SMI_LARB_NONSEC_CON(i));
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}
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}
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static void mtk_smi_larb_config_port_mt8173(struct device *dev)
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{
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struct mtk_smi_larb *larb = dev_get_drvdata(dev);
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writel(*larb->mmu, larb->base + SMI_LARB_MMU_EN);
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}
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static void mtk_smi_larb_config_port_mt8167(struct device *dev)
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{
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struct mtk_smi_larb *larb = dev_get_drvdata(dev);
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writel(*larb->mmu, larb->base + MT8167_SMI_LARB_MMU_EN);
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}
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static void mtk_smi_larb_config_port_gen1(struct device *dev)
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{
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struct mtk_smi_larb *larb = dev_get_drvdata(dev);
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const struct mtk_smi_larb_gen *larb_gen = larb->larb_gen;
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struct mtk_smi *common = dev_get_drvdata(larb->smi_common_dev);
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int i, m4u_port_id, larb_port_num;
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u32 sec_con_val, reg_val;
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m4u_port_id = larb_gen->port_in_larb[larb->larbid];
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larb_port_num = larb_gen->port_in_larb[larb->larbid + 1]
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- larb_gen->port_in_larb[larb->larbid];
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for (i = 0; i < larb_port_num; i++, m4u_port_id++) {
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if (*larb->mmu & BIT(i)) {
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/* bit[port + 3] controls the virtual or physical */
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sec_con_val = SMI_SECUR_CON_VAL_VIRT(m4u_port_id);
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} else {
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/* do not need to enable m4u for this port */
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continue;
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}
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reg_val = readl(common->smi_ao_base
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+ REG_SMI_SECUR_CON_ADDR(m4u_port_id));
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reg_val &= SMI_SECUR_CON_VAL_MSK(m4u_port_id);
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reg_val |= sec_con_val;
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reg_val |= SMI_SECUR_CON_VAL_DOMAIN(m4u_port_id);
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writel(reg_val,
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common->smi_ao_base
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+ REG_SMI_SECUR_CON_ADDR(m4u_port_id));
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}
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}
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static void
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mtk_smi_larb_unbind(struct device *dev, struct device *master, void *data)
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{
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/* Do nothing as the iommu is always enabled. */
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}
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static const struct component_ops mtk_smi_larb_component_ops = {
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.bind = mtk_smi_larb_bind,
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.unbind = mtk_smi_larb_unbind,
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};
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static const struct mtk_smi_larb_gen mtk_smi_larb_mt8173 = {
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/* mt8173 do not need the port in larb */
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.config_port = mtk_smi_larb_config_port_mt8173,
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};
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static const struct mtk_smi_larb_gen mtk_smi_larb_mt8167 = {
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/* mt8167 do not need the port in larb */
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.config_port = mtk_smi_larb_config_port_mt8167,
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};
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static const struct mtk_smi_larb_gen mtk_smi_larb_mt2701 = {
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.port_in_larb = {
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LARB0_PORT_OFFSET, LARB1_PORT_OFFSET,
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LARB2_PORT_OFFSET, LARB3_PORT_OFFSET
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},
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.config_port = mtk_smi_larb_config_port_gen1,
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};
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static const struct mtk_smi_larb_gen mtk_smi_larb_mt2712 = {
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.config_port = mtk_smi_larb_config_port_gen2_general,
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.larb_direct_to_common_mask = BIT(8) | BIT(9), /* bdpsys */
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};
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static const struct mtk_smi_larb_gen mtk_smi_larb_mt6779 = {
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.config_port = mtk_smi_larb_config_port_gen2_general,
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.larb_direct_to_common_mask =
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BIT(4) | BIT(6) | BIT(11) | BIT(12) | BIT(13),
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/* DUMMY | IPU0 | IPU1 | CCU | MDLA */
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};
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static const struct mtk_smi_larb_gen mtk_smi_larb_mt8183 = {
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.has_gals = true,
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.config_port = mtk_smi_larb_config_port_gen2_general,
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.larb_direct_to_common_mask = BIT(2) | BIT(3) | BIT(7),
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/* IPU0 | IPU1 | CCU */
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};
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static const struct mtk_smi_larb_gen mtk_smi_larb_mt8192 = {
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.config_port = mtk_smi_larb_config_port_gen2_general,
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};
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static const struct of_device_id mtk_smi_larb_of_ids[] = {
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{
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.compatible = "mediatek,mt8167-smi-larb",
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.data = &mtk_smi_larb_mt8167
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},
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{
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.compatible = "mediatek,mt8173-smi-larb",
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.data = &mtk_smi_larb_mt8173
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},
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{
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.compatible = "mediatek,mt2701-smi-larb",
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.data = &mtk_smi_larb_mt2701
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},
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{
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.compatible = "mediatek,mt2712-smi-larb",
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.data = &mtk_smi_larb_mt2712
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},
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{
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.compatible = "mediatek,mt6779-smi-larb",
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.data = &mtk_smi_larb_mt6779
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},
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{
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.compatible = "mediatek,mt8183-smi-larb",
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.data = &mtk_smi_larb_mt8183
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},
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{
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.compatible = "mediatek,mt8192-smi-larb",
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.data = &mtk_smi_larb_mt8192
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},
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{}
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};
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static int mtk_smi_larb_probe(struct platform_device *pdev)
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{
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struct mtk_smi_larb *larb;
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struct resource *res;
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struct device *dev = &pdev->dev;
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struct device_node *smi_node;
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struct platform_device *smi_pdev;
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larb = devm_kzalloc(dev, sizeof(*larb), GFP_KERNEL);
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if (!larb)
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return -ENOMEM;
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larb->larb_gen = of_device_get_match_data(dev);
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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larb->base = devm_ioremap_resource(dev, res);
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if (IS_ERR(larb->base))
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return PTR_ERR(larb->base);
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larb->smi.clk_apb = devm_clk_get(dev, "apb");
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if (IS_ERR(larb->smi.clk_apb))
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return PTR_ERR(larb->smi.clk_apb);
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larb->smi.clk_smi = devm_clk_get(dev, "smi");
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if (IS_ERR(larb->smi.clk_smi))
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return PTR_ERR(larb->smi.clk_smi);
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if (larb->larb_gen->has_gals) {
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/* The larbs may still haven't gals even if the SoC support.*/
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larb->smi.clk_gals0 = devm_clk_get(dev, "gals");
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if (PTR_ERR(larb->smi.clk_gals0) == -ENOENT)
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larb->smi.clk_gals0 = NULL;
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else if (IS_ERR(larb->smi.clk_gals0))
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return PTR_ERR(larb->smi.clk_gals0);
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}
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larb->smi.dev = dev;
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smi_node = of_parse_phandle(dev->of_node, "mediatek,smi", 0);
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if (!smi_node)
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return -EINVAL;
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smi_pdev = of_find_device_by_node(smi_node);
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of_node_put(smi_node);
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if (smi_pdev) {
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if (!platform_get_drvdata(smi_pdev))
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return -EPROBE_DEFER;
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larb->smi_common_dev = &smi_pdev->dev;
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} else {
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dev_err(dev, "Failed to get the smi_common device\n");
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return -EINVAL;
|
|
}
|
|
|
|
pm_runtime_enable(dev);
|
|
platform_set_drvdata(pdev, larb);
|
|
return component_add(dev, &mtk_smi_larb_component_ops);
|
|
}
|
|
|
|
static int mtk_smi_larb_remove(struct platform_device *pdev)
|
|
{
|
|
pm_runtime_disable(&pdev->dev);
|
|
component_del(&pdev->dev, &mtk_smi_larb_component_ops);
|
|
return 0;
|
|
}
|
|
|
|
static int __maybe_unused mtk_smi_larb_resume(struct device *dev)
|
|
{
|
|
struct mtk_smi_larb *larb = dev_get_drvdata(dev);
|
|
const struct mtk_smi_larb_gen *larb_gen = larb->larb_gen;
|
|
int ret;
|
|
|
|
/* Power on smi-common. */
|
|
ret = pm_runtime_resume_and_get(larb->smi_common_dev);
|
|
if (ret < 0) {
|
|
dev_err(dev, "Failed to pm get for smi-common(%d).\n", ret);
|
|
return ret;
|
|
}
|
|
|
|
ret = mtk_smi_clk_enable(&larb->smi);
|
|
if (ret < 0) {
|
|
dev_err(dev, "Failed to enable clock(%d).\n", ret);
|
|
pm_runtime_put_sync(larb->smi_common_dev);
|
|
return ret;
|
|
}
|
|
|
|
/* Configure the basic setting for this larb */
|
|
larb_gen->config_port(dev);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int __maybe_unused mtk_smi_larb_suspend(struct device *dev)
|
|
{
|
|
struct mtk_smi_larb *larb = dev_get_drvdata(dev);
|
|
|
|
mtk_smi_clk_disable(&larb->smi);
|
|
pm_runtime_put_sync(larb->smi_common_dev);
|
|
return 0;
|
|
}
|
|
|
|
static const struct dev_pm_ops smi_larb_pm_ops = {
|
|
SET_RUNTIME_PM_OPS(mtk_smi_larb_suspend, mtk_smi_larb_resume, NULL)
|
|
SET_LATE_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
|
|
pm_runtime_force_resume)
|
|
};
|
|
|
|
static struct platform_driver mtk_smi_larb_driver = {
|
|
.probe = mtk_smi_larb_probe,
|
|
.remove = mtk_smi_larb_remove,
|
|
.driver = {
|
|
.name = "mtk-smi-larb",
|
|
.of_match_table = mtk_smi_larb_of_ids,
|
|
.pm = &smi_larb_pm_ops,
|
|
}
|
|
};
|
|
|
|
static const struct mtk_smi_common_plat mtk_smi_common_gen1 = {
|
|
.gen = MTK_SMI_GEN1,
|
|
};
|
|
|
|
static const struct mtk_smi_common_plat mtk_smi_common_gen2 = {
|
|
.gen = MTK_SMI_GEN2,
|
|
};
|
|
|
|
static const struct mtk_smi_common_plat mtk_smi_common_mt6779 = {
|
|
.gen = MTK_SMI_GEN2,
|
|
.has_gals = true,
|
|
.bus_sel = F_MMU1_LARB(1) | F_MMU1_LARB(2) | F_MMU1_LARB(4) |
|
|
F_MMU1_LARB(5) | F_MMU1_LARB(6) | F_MMU1_LARB(7),
|
|
};
|
|
|
|
static const struct mtk_smi_common_plat mtk_smi_common_mt8183 = {
|
|
.gen = MTK_SMI_GEN2,
|
|
.has_gals = true,
|
|
.bus_sel = F_MMU1_LARB(1) | F_MMU1_LARB(2) | F_MMU1_LARB(5) |
|
|
F_MMU1_LARB(7),
|
|
};
|
|
|
|
static const struct mtk_smi_common_plat mtk_smi_common_mt8192 = {
|
|
.gen = MTK_SMI_GEN2,
|
|
.has_gals = true,
|
|
.bus_sel = F_MMU1_LARB(1) | F_MMU1_LARB(2) | F_MMU1_LARB(5) |
|
|
F_MMU1_LARB(6),
|
|
};
|
|
|
|
static const struct of_device_id mtk_smi_common_of_ids[] = {
|
|
{
|
|
.compatible = "mediatek,mt8173-smi-common",
|
|
.data = &mtk_smi_common_gen2,
|
|
},
|
|
{
|
|
.compatible = "mediatek,mt8167-smi-common",
|
|
.data = &mtk_smi_common_gen2,
|
|
},
|
|
{
|
|
.compatible = "mediatek,mt2701-smi-common",
|
|
.data = &mtk_smi_common_gen1,
|
|
},
|
|
{
|
|
.compatible = "mediatek,mt2712-smi-common",
|
|
.data = &mtk_smi_common_gen2,
|
|
},
|
|
{
|
|
.compatible = "mediatek,mt6779-smi-common",
|
|
.data = &mtk_smi_common_mt6779,
|
|
},
|
|
{
|
|
.compatible = "mediatek,mt8183-smi-common",
|
|
.data = &mtk_smi_common_mt8183,
|
|
},
|
|
{
|
|
.compatible = "mediatek,mt8192-smi-common",
|
|
.data = &mtk_smi_common_mt8192,
|
|
},
|
|
{}
|
|
};
|
|
|
|
static int mtk_smi_common_probe(struct platform_device *pdev)
|
|
{
|
|
struct device *dev = &pdev->dev;
|
|
struct mtk_smi *common;
|
|
struct resource *res;
|
|
int ret;
|
|
|
|
common = devm_kzalloc(dev, sizeof(*common), GFP_KERNEL);
|
|
if (!common)
|
|
return -ENOMEM;
|
|
common->dev = dev;
|
|
common->plat = of_device_get_match_data(dev);
|
|
|
|
common->clk_apb = devm_clk_get(dev, "apb");
|
|
if (IS_ERR(common->clk_apb))
|
|
return PTR_ERR(common->clk_apb);
|
|
|
|
common->clk_smi = devm_clk_get(dev, "smi");
|
|
if (IS_ERR(common->clk_smi))
|
|
return PTR_ERR(common->clk_smi);
|
|
|
|
if (common->plat->has_gals) {
|
|
common->clk_gals0 = devm_clk_get(dev, "gals0");
|
|
if (IS_ERR(common->clk_gals0))
|
|
return PTR_ERR(common->clk_gals0);
|
|
|
|
common->clk_gals1 = devm_clk_get(dev, "gals1");
|
|
if (IS_ERR(common->clk_gals1))
|
|
return PTR_ERR(common->clk_gals1);
|
|
}
|
|
|
|
/*
|
|
* for mtk smi gen 1, we need to get the ao(always on) base to config
|
|
* m4u port, and we need to enable the aync clock for transform the smi
|
|
* clock into emi clock domain, but for mtk smi gen2, there's no smi ao
|
|
* base.
|
|
*/
|
|
if (common->plat->gen == MTK_SMI_GEN1) {
|
|
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
common->smi_ao_base = devm_ioremap_resource(dev, res);
|
|
if (IS_ERR(common->smi_ao_base))
|
|
return PTR_ERR(common->smi_ao_base);
|
|
|
|
common->clk_async = devm_clk_get(dev, "async");
|
|
if (IS_ERR(common->clk_async))
|
|
return PTR_ERR(common->clk_async);
|
|
|
|
ret = clk_prepare_enable(common->clk_async);
|
|
if (ret)
|
|
return ret;
|
|
} else {
|
|
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
common->base = devm_ioremap_resource(dev, res);
|
|
if (IS_ERR(common->base))
|
|
return PTR_ERR(common->base);
|
|
}
|
|
pm_runtime_enable(dev);
|
|
platform_set_drvdata(pdev, common);
|
|
return 0;
|
|
}
|
|
|
|
static int mtk_smi_common_remove(struct platform_device *pdev)
|
|
{
|
|
pm_runtime_disable(&pdev->dev);
|
|
return 0;
|
|
}
|
|
|
|
static int __maybe_unused mtk_smi_common_resume(struct device *dev)
|
|
{
|
|
struct mtk_smi *common = dev_get_drvdata(dev);
|
|
u32 bus_sel = common->plat->bus_sel;
|
|
int ret;
|
|
|
|
ret = mtk_smi_clk_enable(common);
|
|
if (ret) {
|
|
dev_err(common->dev, "Failed to enable clock(%d).\n", ret);
|
|
return ret;
|
|
}
|
|
|
|
if (common->plat->gen == MTK_SMI_GEN2 && bus_sel)
|
|
writel(bus_sel, common->base + SMI_BUS_SEL);
|
|
return 0;
|
|
}
|
|
|
|
static int __maybe_unused mtk_smi_common_suspend(struct device *dev)
|
|
{
|
|
struct mtk_smi *common = dev_get_drvdata(dev);
|
|
|
|
mtk_smi_clk_disable(common);
|
|
return 0;
|
|
}
|
|
|
|
static const struct dev_pm_ops smi_common_pm_ops = {
|
|
SET_RUNTIME_PM_OPS(mtk_smi_common_suspend, mtk_smi_common_resume, NULL)
|
|
SET_LATE_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
|
|
pm_runtime_force_resume)
|
|
};
|
|
|
|
static struct platform_driver mtk_smi_common_driver = {
|
|
.probe = mtk_smi_common_probe,
|
|
.remove = mtk_smi_common_remove,
|
|
.driver = {
|
|
.name = "mtk-smi-common",
|
|
.of_match_table = mtk_smi_common_of_ids,
|
|
.pm = &smi_common_pm_ops,
|
|
}
|
|
};
|
|
|
|
static struct platform_driver * const smidrivers[] = {
|
|
&mtk_smi_common_driver,
|
|
&mtk_smi_larb_driver,
|
|
};
|
|
|
|
static int __init mtk_smi_init(void)
|
|
{
|
|
return platform_register_drivers(smidrivers, ARRAY_SIZE(smidrivers));
|
|
}
|
|
module_init(mtk_smi_init);
|
|
|
|
static void __exit mtk_smi_exit(void)
|
|
{
|
|
platform_unregister_drivers(smidrivers, ARRAY_SIZE(smidrivers));
|
|
}
|
|
module_exit(mtk_smi_exit);
|
|
|
|
MODULE_DESCRIPTION("MediaTek SMI driver");
|
|
MODULE_LICENSE("GPL v2");
|