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![Thierry Reding](/assets/img/avatar_default.png)
Instead of using a mix of -EOPNOTSUPP and -ENOTSUPP, use the more standard -EINVAL to signal that the specified polarity value was invalid. Acked-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Acked-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
197 lines
4.9 KiB
C
197 lines
4.9 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (C) 2015 Intel Corporation. All rights reserved.
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*
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* Author: Shobhit Kumar <shobhit.kumar@intel.com>
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*/
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#include <linux/platform_device.h>
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#include <linux/regmap.h>
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#include <linux/mfd/intel_soc_pmic.h>
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#include <linux/pwm.h>
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#define PWM0_CLK_DIV 0x4B
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#define PWM_OUTPUT_ENABLE BIT(7)
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#define PWM_DIV_CLK_0 0x00 /* DIVIDECLK = BASECLK */
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#define PWM_DIV_CLK_100 0x63 /* DIVIDECLK = BASECLK/100 */
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#define PWM_DIV_CLK_128 0x7F /* DIVIDECLK = BASECLK/128 */
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#define PWM0_DUTY_CYCLE 0x4E
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#define BACKLIGHT_EN 0x51
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#define PWM_MAX_LEVEL 0xFF
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#define PWM_BASE_CLK_MHZ 6 /* 6 MHz */
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#define PWM_MAX_PERIOD_NS 5461334 /* 183 Hz */
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/**
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* struct crystalcove_pwm - Crystal Cove PWM controller
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* @chip: the abstract pwm_chip structure.
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* @regmap: the regmap from the parent device.
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*/
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struct crystalcove_pwm {
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struct pwm_chip chip;
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struct regmap *regmap;
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};
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static inline struct crystalcove_pwm *to_crc_pwm(struct pwm_chip *pc)
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{
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return container_of(pc, struct crystalcove_pwm, chip);
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}
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static int crc_pwm_calc_clk_div(int period_ns)
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{
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int clk_div;
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clk_div = PWM_BASE_CLK_MHZ * period_ns / (256 * NSEC_PER_USEC);
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/* clk_div 1 - 128, maps to register values 0-127 */
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if (clk_div > 0)
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clk_div--;
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return clk_div;
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}
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static int crc_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
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const struct pwm_state *state)
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{
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struct crystalcove_pwm *crc_pwm = to_crc_pwm(chip);
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struct device *dev = crc_pwm->chip.dev;
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int err;
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if (state->period > PWM_MAX_PERIOD_NS) {
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dev_err(dev, "un-supported period_ns\n");
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return -EINVAL;
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}
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if (state->polarity != PWM_POLARITY_NORMAL)
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return -EINVAL;
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if (pwm_is_enabled(pwm) && !state->enabled) {
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err = regmap_write(crc_pwm->regmap, BACKLIGHT_EN, 0);
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if (err) {
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dev_err(dev, "Error writing BACKLIGHT_EN %d\n", err);
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return err;
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}
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}
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if (pwm_get_duty_cycle(pwm) != state->duty_cycle ||
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pwm_get_period(pwm) != state->period) {
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u64 level = state->duty_cycle * PWM_MAX_LEVEL;
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do_div(level, state->period);
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err = regmap_write(crc_pwm->regmap, PWM0_DUTY_CYCLE, level);
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if (err) {
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dev_err(dev, "Error writing PWM0_DUTY_CYCLE %d\n", err);
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return err;
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}
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}
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if (pwm_is_enabled(pwm) && state->enabled &&
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pwm_get_period(pwm) != state->period) {
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/* changing the clk divisor, clear PWM_OUTPUT_ENABLE first */
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err = regmap_write(crc_pwm->regmap, PWM0_CLK_DIV, 0);
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if (err) {
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dev_err(dev, "Error writing PWM0_CLK_DIV %d\n", err);
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return err;
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}
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}
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if (pwm_get_period(pwm) != state->period ||
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pwm_is_enabled(pwm) != state->enabled) {
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int clk_div = crc_pwm_calc_clk_div(state->period);
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int pwm_output_enable = state->enabled ? PWM_OUTPUT_ENABLE : 0;
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err = regmap_write(crc_pwm->regmap, PWM0_CLK_DIV,
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clk_div | pwm_output_enable);
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if (err) {
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dev_err(dev, "Error writing PWM0_CLK_DIV %d\n", err);
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return err;
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}
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}
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if (!pwm_is_enabled(pwm) && state->enabled) {
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err = regmap_write(crc_pwm->regmap, BACKLIGHT_EN, 1);
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if (err) {
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dev_err(dev, "Error writing BACKLIGHT_EN %d\n", err);
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return err;
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}
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}
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return 0;
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}
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static void crc_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm,
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struct pwm_state *state)
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{
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struct crystalcove_pwm *crc_pwm = to_crc_pwm(chip);
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struct device *dev = crc_pwm->chip.dev;
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unsigned int clk_div, clk_div_reg, duty_cycle_reg;
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int error;
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error = regmap_read(crc_pwm->regmap, PWM0_CLK_DIV, &clk_div_reg);
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if (error) {
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dev_err(dev, "Error reading PWM0_CLK_DIV %d\n", error);
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return;
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}
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error = regmap_read(crc_pwm->regmap, PWM0_DUTY_CYCLE, &duty_cycle_reg);
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if (error) {
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dev_err(dev, "Error reading PWM0_DUTY_CYCLE %d\n", error);
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return;
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}
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clk_div = (clk_div_reg & ~PWM_OUTPUT_ENABLE) + 1;
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state->period =
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DIV_ROUND_UP(clk_div * NSEC_PER_USEC * 256, PWM_BASE_CLK_MHZ);
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state->duty_cycle =
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DIV_ROUND_UP_ULL(duty_cycle_reg * state->period, PWM_MAX_LEVEL);
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state->polarity = PWM_POLARITY_NORMAL;
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state->enabled = !!(clk_div_reg & PWM_OUTPUT_ENABLE);
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}
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static const struct pwm_ops crc_pwm_ops = {
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.apply = crc_pwm_apply,
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.get_state = crc_pwm_get_state,
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};
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static int crystalcove_pwm_probe(struct platform_device *pdev)
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{
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struct crystalcove_pwm *pwm;
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struct device *dev = pdev->dev.parent;
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struct intel_soc_pmic *pmic = dev_get_drvdata(dev);
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pwm = devm_kzalloc(&pdev->dev, sizeof(*pwm), GFP_KERNEL);
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if (!pwm)
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return -ENOMEM;
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pwm->chip.dev = &pdev->dev;
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pwm->chip.ops = &crc_pwm_ops;
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pwm->chip.base = -1;
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pwm->chip.npwm = 1;
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/* get the PMIC regmap */
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pwm->regmap = pmic->regmap;
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platform_set_drvdata(pdev, pwm);
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return pwmchip_add(&pwm->chip);
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}
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static int crystalcove_pwm_remove(struct platform_device *pdev)
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{
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struct crystalcove_pwm *pwm = platform_get_drvdata(pdev);
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return pwmchip_remove(&pwm->chip);
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}
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static struct platform_driver crystalcove_pwm_driver = {
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.probe = crystalcove_pwm_probe,
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.remove = crystalcove_pwm_remove,
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.driver = {
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.name = "crystal_cove_pwm",
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},
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};
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builtin_platform_driver(crystalcove_pwm_driver);
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