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![Linus Walleij](/assets/img/avatar_default.png)
This converts the PPC4xx SPI driver to use GPIO descriptors. The driver is already just picking some GPIOs from the device tree so the conversion is pretty straight forward. However this driver is looking form a pure "gpios" property rather than the standard binding "cs-gpios" so we need to add a new exception to the gpiolib OF parser to allow this for this driver's compatibles. Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Cc: linuxppc-dev@lists.ozlabs.org Link: https://lore.kernel.org/r/20200714072226.26071-1-linus.walleij@linaro.org Signed-off-by: Mark Brown <broonie@kernel.org>
499 lines
12 KiB
C
499 lines
12 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* SPI_PPC4XX SPI controller driver.
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*
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* Copyright (C) 2007 Gary Jennejohn <garyj@denx.de>
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* Copyright 2008 Stefan Roese <sr@denx.de>, DENX Software Engineering
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* Copyright 2009 Harris Corporation, Steven A. Falco <sfalco@harris.com>
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*
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* Based in part on drivers/spi/spi_s3c24xx.c
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*
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* Copyright (c) 2006 Ben Dooks
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* Copyright (c) 2006 Simtec Electronics
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* Ben Dooks <ben@simtec.co.uk>
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*/
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/*
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* The PPC4xx SPI controller has no FIFO so each sent/received byte will
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* generate an interrupt to the CPU. This can cause high CPU utilization.
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* This driver allows platforms to reduce the interrupt load on the CPU
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* during SPI transfers by setting max_speed_hz via the device tree.
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*/
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#include <linux/module.h>
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#include <linux/sched.h>
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#include <linux/slab.h>
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#include <linux/errno.h>
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#include <linux/wait.h>
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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#include <linux/of_platform.h>
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#include <linux/interrupt.h>
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#include <linux/delay.h>
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#include <linux/spi/spi.h>
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#include <linux/spi/spi_bitbang.h>
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#include <asm/io.h>
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#include <asm/dcr.h>
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#include <asm/dcr-regs.h>
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/* bits in mode register - bit 0 is MSb */
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/*
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* SPI_PPC4XX_MODE_SCP = 0 means "data latched on trailing edge of clock"
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* SPI_PPC4XX_MODE_SCP = 1 means "data latched on leading edge of clock"
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* Note: This is the inverse of CPHA.
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*/
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#define SPI_PPC4XX_MODE_SCP (0x80 >> 3)
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/* SPI_PPC4XX_MODE_SPE = 1 means "port enabled" */
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#define SPI_PPC4XX_MODE_SPE (0x80 >> 4)
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/*
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* SPI_PPC4XX_MODE_RD = 0 means "MSB first" - this is the normal mode
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* SPI_PPC4XX_MODE_RD = 1 means "LSB first" - this is bit-reversed mode
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* Note: This is identical to SPI_LSB_FIRST.
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*/
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#define SPI_PPC4XX_MODE_RD (0x80 >> 5)
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/*
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* SPI_PPC4XX_MODE_CI = 0 means "clock idles low"
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* SPI_PPC4XX_MODE_CI = 1 means "clock idles high"
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* Note: This is identical to CPOL.
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*/
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#define SPI_PPC4XX_MODE_CI (0x80 >> 6)
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/*
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* SPI_PPC4XX_MODE_IL = 0 means "loopback disable"
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* SPI_PPC4XX_MODE_IL = 1 means "loopback enable"
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*/
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#define SPI_PPC4XX_MODE_IL (0x80 >> 7)
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/* bits in control register */
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/* starts a transfer when set */
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#define SPI_PPC4XX_CR_STR (0x80 >> 7)
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/* bits in status register */
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/* port is busy with a transfer */
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#define SPI_PPC4XX_SR_BSY (0x80 >> 6)
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/* RxD ready */
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#define SPI_PPC4XX_SR_RBR (0x80 >> 7)
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/* clock settings (SCP and CI) for various SPI modes */
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#define SPI_CLK_MODE0 (SPI_PPC4XX_MODE_SCP | 0)
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#define SPI_CLK_MODE1 (0 | 0)
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#define SPI_CLK_MODE2 (SPI_PPC4XX_MODE_SCP | SPI_PPC4XX_MODE_CI)
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#define SPI_CLK_MODE3 (0 | SPI_PPC4XX_MODE_CI)
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#define DRIVER_NAME "spi_ppc4xx_of"
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struct spi_ppc4xx_regs {
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u8 mode;
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u8 rxd;
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u8 txd;
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u8 cr;
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u8 sr;
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u8 dummy;
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/*
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* Clock divisor modulus register
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* This uses the following formula:
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* SCPClkOut = OPBCLK/(4(CDM + 1))
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* or
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* CDM = (OPBCLK/4*SCPClkOut) - 1
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* bit 0 is the MSb!
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*/
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u8 cdm;
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};
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/* SPI Controller driver's private data. */
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struct ppc4xx_spi {
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/* bitbang has to be first */
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struct spi_bitbang bitbang;
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struct completion done;
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u64 mapbase;
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u64 mapsize;
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int irqnum;
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/* need this to set the SPI clock */
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unsigned int opb_freq;
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/* for transfers */
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int len;
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int count;
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/* data buffers */
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const unsigned char *tx;
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unsigned char *rx;
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struct spi_ppc4xx_regs __iomem *regs; /* pointer to the registers */
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struct spi_master *master;
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struct device *dev;
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};
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/* need this so we can set the clock in the chipselect routine */
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struct spi_ppc4xx_cs {
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u8 mode;
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};
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static int spi_ppc4xx_txrx(struct spi_device *spi, struct spi_transfer *t)
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{
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struct ppc4xx_spi *hw;
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u8 data;
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dev_dbg(&spi->dev, "txrx: tx %p, rx %p, len %d\n",
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t->tx_buf, t->rx_buf, t->len);
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hw = spi_master_get_devdata(spi->master);
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hw->tx = t->tx_buf;
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hw->rx = t->rx_buf;
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hw->len = t->len;
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hw->count = 0;
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/* send the first byte */
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data = hw->tx ? hw->tx[0] : 0;
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out_8(&hw->regs->txd, data);
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out_8(&hw->regs->cr, SPI_PPC4XX_CR_STR);
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wait_for_completion(&hw->done);
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return hw->count;
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}
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static int spi_ppc4xx_setupxfer(struct spi_device *spi, struct spi_transfer *t)
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{
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struct ppc4xx_spi *hw = spi_master_get_devdata(spi->master);
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struct spi_ppc4xx_cs *cs = spi->controller_state;
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int scr;
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u8 cdm = 0;
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u32 speed;
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u8 bits_per_word;
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/* Start with the generic configuration for this device. */
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bits_per_word = spi->bits_per_word;
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speed = spi->max_speed_hz;
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/*
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* Modify the configuration if the transfer overrides it. Do not allow
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* the transfer to overwrite the generic configuration with zeros.
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*/
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if (t) {
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if (t->bits_per_word)
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bits_per_word = t->bits_per_word;
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if (t->speed_hz)
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speed = min(t->speed_hz, spi->max_speed_hz);
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}
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if (!speed || (speed > spi->max_speed_hz)) {
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dev_err(&spi->dev, "invalid speed_hz (%d)\n", speed);
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return -EINVAL;
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}
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/* Write new configuration */
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out_8(&hw->regs->mode, cs->mode);
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/* Set the clock */
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/* opb_freq was already divided by 4 */
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scr = (hw->opb_freq / speed) - 1;
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if (scr > 0)
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cdm = min(scr, 0xff);
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dev_dbg(&spi->dev, "setting pre-scaler to %d (hz %d)\n", cdm, speed);
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if (in_8(&hw->regs->cdm) != cdm)
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out_8(&hw->regs->cdm, cdm);
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mutex_lock(&hw->bitbang.lock);
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if (!hw->bitbang.busy) {
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hw->bitbang.chipselect(spi, BITBANG_CS_INACTIVE);
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/* Need to ndelay here? */
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}
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mutex_unlock(&hw->bitbang.lock);
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return 0;
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}
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static int spi_ppc4xx_setup(struct spi_device *spi)
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{
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struct spi_ppc4xx_cs *cs = spi->controller_state;
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if (!spi->max_speed_hz) {
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dev_err(&spi->dev, "invalid max_speed_hz (must be non-zero)\n");
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return -EINVAL;
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}
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if (cs == NULL) {
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cs = kzalloc(sizeof *cs, GFP_KERNEL);
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if (!cs)
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return -ENOMEM;
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spi->controller_state = cs;
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}
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/*
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* We set all bits of the SPI0_MODE register, so,
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* no need to read-modify-write
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*/
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cs->mode = SPI_PPC4XX_MODE_SPE;
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switch (spi->mode & (SPI_CPHA | SPI_CPOL)) {
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case SPI_MODE_0:
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cs->mode |= SPI_CLK_MODE0;
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break;
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case SPI_MODE_1:
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cs->mode |= SPI_CLK_MODE1;
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break;
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case SPI_MODE_2:
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cs->mode |= SPI_CLK_MODE2;
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break;
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case SPI_MODE_3:
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cs->mode |= SPI_CLK_MODE3;
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break;
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}
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if (spi->mode & SPI_LSB_FIRST)
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cs->mode |= SPI_PPC4XX_MODE_RD;
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return 0;
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}
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static irqreturn_t spi_ppc4xx_int(int irq, void *dev_id)
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{
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struct ppc4xx_spi *hw;
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u8 status;
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u8 data;
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unsigned int count;
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hw = (struct ppc4xx_spi *)dev_id;
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status = in_8(&hw->regs->sr);
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if (!status)
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return IRQ_NONE;
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/*
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* BSY de-asserts one cycle after the transfer is complete. The
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* interrupt is asserted after the transfer is complete. The exact
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* relationship is not documented, hence this code.
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*/
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if (unlikely(status & SPI_PPC4XX_SR_BSY)) {
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u8 lstatus;
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int cnt = 0;
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dev_dbg(hw->dev, "got interrupt but spi still busy?\n");
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do {
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ndelay(10);
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lstatus = in_8(&hw->regs->sr);
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} while (++cnt < 100 && lstatus & SPI_PPC4XX_SR_BSY);
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if (cnt >= 100) {
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dev_err(hw->dev, "busywait: too many loops!\n");
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complete(&hw->done);
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return IRQ_HANDLED;
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} else {
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/* status is always 1 (RBR) here */
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status = in_8(&hw->regs->sr);
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dev_dbg(hw->dev, "loops %d status %x\n", cnt, status);
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}
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}
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count = hw->count;
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hw->count++;
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/* RBR triggered this interrupt. Therefore, data must be ready. */
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data = in_8(&hw->regs->rxd);
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if (hw->rx)
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hw->rx[count] = data;
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count++;
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if (count < hw->len) {
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data = hw->tx ? hw->tx[count] : 0;
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out_8(&hw->regs->txd, data);
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out_8(&hw->regs->cr, SPI_PPC4XX_CR_STR);
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} else {
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complete(&hw->done);
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}
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return IRQ_HANDLED;
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}
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static void spi_ppc4xx_cleanup(struct spi_device *spi)
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{
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kfree(spi->controller_state);
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}
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static void spi_ppc4xx_enable(struct ppc4xx_spi *hw)
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{
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/*
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* On all 4xx PPC's the SPI bus is shared/multiplexed with
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* the 2nd I2C bus. We need to enable the the SPI bus before
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* using it.
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*/
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/* need to clear bit 14 to enable SPC */
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dcri_clrset(SDR0, SDR0_PFC1, 0x80000000 >> 14, 0);
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}
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/*
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* platform_device layer stuff...
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*/
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static int spi_ppc4xx_of_probe(struct platform_device *op)
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{
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struct ppc4xx_spi *hw;
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struct spi_master *master;
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struct spi_bitbang *bbp;
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struct resource resource;
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struct device_node *np = op->dev.of_node;
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struct device *dev = &op->dev;
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struct device_node *opbnp;
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int ret;
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const unsigned int *clk;
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master = spi_alloc_master(dev, sizeof *hw);
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if (master == NULL)
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return -ENOMEM;
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master->dev.of_node = np;
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platform_set_drvdata(op, master);
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hw = spi_master_get_devdata(master);
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hw->master = master;
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hw->dev = dev;
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init_completion(&hw->done);
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/* Setup the state for the bitbang driver */
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bbp = &hw->bitbang;
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bbp->master = hw->master;
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bbp->setup_transfer = spi_ppc4xx_setupxfer;
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bbp->txrx_bufs = spi_ppc4xx_txrx;
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bbp->use_dma = 0;
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bbp->master->setup = spi_ppc4xx_setup;
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bbp->master->cleanup = spi_ppc4xx_cleanup;
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bbp->master->bits_per_word_mask = SPI_BPW_MASK(8);
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bbp->master->use_gpio_descriptors = true;
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/*
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* The SPI core will count the number of GPIO descriptors to figure
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* out the number of chip selects available on the platform.
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*/
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bbp->master->num_chipselect = 0;
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/* the spi->mode bits understood by this driver: */
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bbp->master->mode_bits =
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SPI_CPHA | SPI_CPOL | SPI_CS_HIGH | SPI_LSB_FIRST;
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/* Get the clock for the OPB */
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opbnp = of_find_compatible_node(NULL, NULL, "ibm,opb");
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if (opbnp == NULL) {
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dev_err(dev, "OPB: cannot find node\n");
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ret = -ENODEV;
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goto free_master;
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}
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/* Get the clock (Hz) for the OPB */
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clk = of_get_property(opbnp, "clock-frequency", NULL);
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if (clk == NULL) {
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dev_err(dev, "OPB: no clock-frequency property set\n");
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of_node_put(opbnp);
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ret = -ENODEV;
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goto free_master;
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}
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hw->opb_freq = *clk;
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hw->opb_freq >>= 2;
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of_node_put(opbnp);
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ret = of_address_to_resource(np, 0, &resource);
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if (ret) {
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dev_err(dev, "error while parsing device node resource\n");
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goto free_master;
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}
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hw->mapbase = resource.start;
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hw->mapsize = resource_size(&resource);
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/* Sanity check */
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if (hw->mapsize < sizeof(struct spi_ppc4xx_regs)) {
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dev_err(dev, "too small to map registers\n");
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ret = -EINVAL;
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goto free_master;
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}
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/* Request IRQ */
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hw->irqnum = irq_of_parse_and_map(np, 0);
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ret = request_irq(hw->irqnum, spi_ppc4xx_int,
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0, "spi_ppc4xx_of", (void *)hw);
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if (ret) {
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dev_err(dev, "unable to allocate interrupt\n");
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goto free_master;
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}
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if (!request_mem_region(hw->mapbase, hw->mapsize, DRIVER_NAME)) {
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dev_err(dev, "resource unavailable\n");
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ret = -EBUSY;
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goto request_mem_error;
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}
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hw->regs = ioremap(hw->mapbase, sizeof(struct spi_ppc4xx_regs));
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if (!hw->regs) {
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dev_err(dev, "unable to memory map registers\n");
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ret = -ENXIO;
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goto map_io_error;
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}
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spi_ppc4xx_enable(hw);
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/* Finally register our spi controller */
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dev->dma_mask = 0;
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ret = spi_bitbang_start(bbp);
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if (ret) {
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dev_err(dev, "failed to register SPI master\n");
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goto unmap_regs;
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}
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dev_info(dev, "driver initialized\n");
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return 0;
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unmap_regs:
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iounmap(hw->regs);
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map_io_error:
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release_mem_region(hw->mapbase, hw->mapsize);
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request_mem_error:
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free_irq(hw->irqnum, hw);
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free_master:
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spi_master_put(master);
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dev_err(dev, "initialization failed\n");
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return ret;
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}
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static int spi_ppc4xx_of_remove(struct platform_device *op)
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{
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struct spi_master *master = platform_get_drvdata(op);
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struct ppc4xx_spi *hw = spi_master_get_devdata(master);
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spi_bitbang_stop(&hw->bitbang);
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release_mem_region(hw->mapbase, hw->mapsize);
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free_irq(hw->irqnum, hw);
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iounmap(hw->regs);
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spi_master_put(master);
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return 0;
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}
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static const struct of_device_id spi_ppc4xx_of_match[] = {
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{ .compatible = "ibm,ppc4xx-spi", },
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{},
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};
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MODULE_DEVICE_TABLE(of, spi_ppc4xx_of_match);
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static struct platform_driver spi_ppc4xx_of_driver = {
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.probe = spi_ppc4xx_of_probe,
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.remove = spi_ppc4xx_of_remove,
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.driver = {
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.name = DRIVER_NAME,
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.of_match_table = spi_ppc4xx_of_match,
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},
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};
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module_platform_driver(spi_ppc4xx_of_driver);
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MODULE_AUTHOR("Gary Jennejohn & Stefan Roese");
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MODULE_DESCRIPTION("Simple PPC4xx SPI Driver");
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MODULE_LICENSE("GPL");
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