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https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
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487e873dd3
Remove all sorts of bits we can get rid of. We are now a very simple KMS driver relying on the stolen memory for our framebuffer base (which is for the moment hardcoded). To support multiple frame buffers and some accel bits we will need some kind of memory allocator, possibly a minimal use of GEM. Signed-off-by: Alan Cox <alan@linux.intel.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
639 lines
16 KiB
C
639 lines
16 KiB
C
/**************************************************************************
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* Copyright (c) 2007, Intel Corporation.
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* All Rights Reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
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*
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* Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
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* develop this driver.
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*
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**************************************************************************/
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/*
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*/
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#include <drm/drmP.h>
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#include "psb_drv.h"
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#include "psb_reg.h"
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#include "psb_intel_reg.h"
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#include "psb_powermgmt.h"
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/*
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* inline functions
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*/
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static inline u32
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psb_pipestat(int pipe)
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{
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if (pipe == 0)
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return PIPEASTAT;
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if (pipe == 1)
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return PIPEBSTAT;
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if (pipe == 2)
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return PIPECSTAT;
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BUG();
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}
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static inline u32
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mid_pipe_event(int pipe)
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{
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if (pipe == 0)
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return _PSB_PIPEA_EVENT_FLAG;
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if (pipe == 1)
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return _MDFLD_PIPEB_EVENT_FLAG;
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if (pipe == 2)
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return _MDFLD_PIPEC_EVENT_FLAG;
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BUG();
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}
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static inline u32
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mid_pipe_vsync(int pipe)
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{
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if (pipe == 0)
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return _PSB_VSYNC_PIPEA_FLAG;
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if (pipe == 1)
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return _PSB_VSYNC_PIPEB_FLAG;
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if (pipe == 2)
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return _MDFLD_PIPEC_VBLANK_FLAG;
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BUG();
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}
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static inline u32
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mid_pipeconf(int pipe)
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{
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if (pipe == 0)
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return PIPEACONF;
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if (pipe == 1)
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return PIPEBCONF;
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if (pipe == 2)
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return PIPECCONF;
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BUG();
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}
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void
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psb_enable_pipestat(struct drm_psb_private *dev_priv, int pipe, u32 mask)
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{
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if ((dev_priv->pipestat[pipe] & mask) != mask) {
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u32 reg = psb_pipestat(pipe);
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dev_priv->pipestat[pipe] |= mask;
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/* Enable the interrupt, clear any pending status */
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if (ospm_power_using_hw_begin(OSPM_DISPLAY_ISLAND,
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OSPM_UHB_ONLY_IF_ON)) {
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u32 writeVal = PSB_RVDC32(reg);
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writeVal |= (mask | (mask >> 16));
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PSB_WVDC32(writeVal, reg);
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(void) PSB_RVDC32(reg);
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ospm_power_using_hw_end(OSPM_DISPLAY_ISLAND);
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}
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}
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}
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void
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psb_disable_pipestat(struct drm_psb_private *dev_priv, int pipe, u32 mask)
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{
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if ((dev_priv->pipestat[pipe] & mask) != 0) {
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u32 reg = psb_pipestat(pipe);
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dev_priv->pipestat[pipe] &= ~mask;
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if (ospm_power_using_hw_begin(OSPM_DISPLAY_ISLAND,
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OSPM_UHB_ONLY_IF_ON)) {
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u32 writeVal = PSB_RVDC32(reg);
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writeVal &= ~mask;
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PSB_WVDC32(writeVal, reg);
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(void) PSB_RVDC32(reg);
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ospm_power_using_hw_end(OSPM_DISPLAY_ISLAND);
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}
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}
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}
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void mid_enable_pipe_event(struct drm_psb_private *dev_priv, int pipe)
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{
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if (ospm_power_using_hw_begin(OSPM_DISPLAY_ISLAND,
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OSPM_UHB_ONLY_IF_ON)) {
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u32 pipe_event = mid_pipe_event(pipe);
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dev_priv->vdc_irq_mask |= pipe_event;
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PSB_WVDC32(~dev_priv->vdc_irq_mask, PSB_INT_MASK_R);
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PSB_WVDC32(dev_priv->vdc_irq_mask, PSB_INT_ENABLE_R);
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ospm_power_using_hw_end(OSPM_DISPLAY_ISLAND);
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}
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}
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void mid_disable_pipe_event(struct drm_psb_private *dev_priv, int pipe)
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{
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if (dev_priv->pipestat[pipe] == 0) {
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if (ospm_power_using_hw_begin(OSPM_DISPLAY_ISLAND,
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OSPM_UHB_ONLY_IF_ON)) {
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u32 pipe_event = mid_pipe_event(pipe);
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dev_priv->vdc_irq_mask &= ~pipe_event;
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PSB_WVDC32(~dev_priv->vdc_irq_mask, PSB_INT_MASK_R);
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PSB_WVDC32(dev_priv->vdc_irq_mask, PSB_INT_ENABLE_R);
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ospm_power_using_hw_end(OSPM_DISPLAY_ISLAND);
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}
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}
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}
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/**
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* Display controller interrupt handler for vsync/vblank.
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*
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*/
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static void mid_vblank_handler(struct drm_device *dev, uint32_t pipe)
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{
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drm_handle_vblank(dev, pipe);
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}
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/**
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* Display controller interrupt handler for pipe event.
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*
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*/
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#define WAIT_STATUS_CLEAR_LOOP_COUNT 0xffff
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static void mid_pipe_event_handler(struct drm_device *dev, uint32_t pipe)
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{
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struct drm_psb_private *dev_priv =
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(struct drm_psb_private *) dev->dev_private;
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uint32_t pipe_stat_val = 0;
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uint32_t pipe_stat_reg = psb_pipestat(pipe);
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uint32_t pipe_enable = dev_priv->pipestat[pipe];
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uint32_t pipe_status = dev_priv->pipestat[pipe] >> 16;
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uint32_t i = 0;
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spin_lock(&dev_priv->irqmask_lock);
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pipe_stat_val = PSB_RVDC32(pipe_stat_reg);
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pipe_stat_val &= pipe_enable | pipe_status;
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pipe_stat_val &= pipe_stat_val >> 16;
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spin_unlock(&dev_priv->irqmask_lock);
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/* clear the 2nd level interrupt status bits */
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/**
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* FIXME: shouldn't use while loop here. However, the interrupt
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* status 'sticky' bits cannot be cleared by setting '1' to that
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* bit once...
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*/
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for (i = 0; i < WAIT_STATUS_CLEAR_LOOP_COUNT; i++) {
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PSB_WVDC32(PSB_RVDC32(pipe_stat_reg), pipe_stat_reg);
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(void) PSB_RVDC32(pipe_stat_reg);
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if ((PSB_RVDC32(pipe_stat_reg) & pipe_status) == 0)
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break;
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}
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if (i == WAIT_STATUS_CLEAR_LOOP_COUNT)
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DRM_ERROR("%s, can't clear the status bits in pipe_stat_reg, its value = 0x%x.\n",
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__func__, PSB_RVDC32(pipe_stat_reg));
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if (pipe_stat_val & PIPE_VBLANK_STATUS)
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mid_vblank_handler(dev, pipe);
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if (pipe_stat_val & PIPE_TE_STATUS)
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drm_handle_vblank(dev, pipe);
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}
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/*
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* Display controller interrupt handler.
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*/
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static void psb_vdc_interrupt(struct drm_device *dev, uint32_t vdc_stat)
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{
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if (vdc_stat & _PSB_PIPEA_EVENT_FLAG)
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mid_pipe_event_handler(dev, 0);
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}
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irqreturn_t psb_irq_handler(DRM_IRQ_ARGS)
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{
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struct drm_device *dev = (struct drm_device *) arg;
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struct drm_psb_private *dev_priv =
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(struct drm_psb_private *) dev->dev_private;
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uint32_t vdc_stat, dsp_int = 0, sgx_int = 0;
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int handled = 0;
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spin_lock(&dev_priv->irqmask_lock);
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vdc_stat = PSB_RVDC32(PSB_INT_IDENTITY_R);
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if (vdc_stat & _MDFLD_DISP_ALL_IRQ_FLAG) {
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PSB_DEBUG_IRQ("Got DISP interrupt\n");
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dsp_int = 1;
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}
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if (vdc_stat & _PSB_IRQ_SGX_FLAG) {
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PSB_DEBUG_IRQ("Got SGX interrupt\n");
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sgx_int = 1;
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}
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if (vdc_stat & _PSB_IRQ_MSVDX_FLAG)
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PSB_DEBUG_IRQ("Got MSVDX interrupt\n");
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if (vdc_stat & _LNC_IRQ_TOPAZ_FLAG)
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PSB_DEBUG_IRQ("Got TOPAZ interrupt\n");
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vdc_stat &= dev_priv->vdc_irq_mask;
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spin_unlock(&dev_priv->irqmask_lock);
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if (dsp_int && ospm_power_is_hw_on(OSPM_DISPLAY_ISLAND)) {
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psb_vdc_interrupt(dev, vdc_stat);
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handled = 1;
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}
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if (sgx_int) {
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/* Not expected - we have it masked, shut it up */
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u32 s, s2;
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s = PSB_RSGX32(PSB_CR_EVENT_STATUS);
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s2 = PSB_RSGX32(PSB_CR_EVENT_STATUS2);
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PSB_WSGX32(s, PSB_CR_EVENT_HOST_CLEAR);
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PSB_WSGX32(s2, PSB_CR_EVENT_HOST_CLEAR2);
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/* if s & _PSB_CE_TWOD_COMPLETE we have 2D done but
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we may as well poll even if we add that ! */
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handled = 1;
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}
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PSB_WVDC32(vdc_stat, PSB_INT_IDENTITY_R);
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(void) PSB_RVDC32(PSB_INT_IDENTITY_R);
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DRM_READMEMORYBARRIER();
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if (!handled)
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return IRQ_NONE;
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return IRQ_HANDLED;
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}
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void psb_irq_preinstall(struct drm_device *dev)
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{
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psb_irq_preinstall_islands(dev, OSPM_ALL_ISLANDS);
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}
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/**
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* FIXME: should I remove display irq enable here??
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*/
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void psb_irq_preinstall_islands(struct drm_device *dev, int hw_islands)
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{
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struct drm_psb_private *dev_priv =
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(struct drm_psb_private *) dev->dev_private;
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unsigned long irqflags;
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PSB_DEBUG_ENTRY("\n");
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spin_lock_irqsave(&dev_priv->irqmask_lock, irqflags);
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if (hw_islands & OSPM_DISPLAY_ISLAND) {
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if (ospm_power_is_hw_on(OSPM_DISPLAY_ISLAND)) {
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PSB_WVDC32(0xFFFFFFFF, PSB_HWSTAM);
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if (dev->vblank_enabled[0])
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dev_priv->vdc_irq_mask |=
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_PSB_PIPEA_EVENT_FLAG;
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if (dev->vblank_enabled[1])
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dev_priv->vdc_irq_mask |=
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_MDFLD_PIPEB_EVENT_FLAG;
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if (dev->vblank_enabled[2])
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dev_priv->vdc_irq_mask |=
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_MDFLD_PIPEC_EVENT_FLAG;
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}
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}
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/* NO I DONT WANT ANY IRQS GRRR FIXMEAC */
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if (hw_islands & OSPM_GRAPHICS_ISLAND)
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dev_priv->vdc_irq_mask |= _PSB_IRQ_SGX_FLAG;
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/* */
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/*This register is safe even if display island is off*/
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PSB_WVDC32(~dev_priv->vdc_irq_mask, PSB_INT_MASK_R);
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spin_unlock_irqrestore(&dev_priv->irqmask_lock, irqflags);
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}
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int psb_irq_postinstall(struct drm_device *dev)
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{
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return psb_irq_postinstall_islands(dev, OSPM_ALL_ISLANDS);
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}
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int psb_irq_postinstall_islands(struct drm_device *dev, int hw_islands)
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{
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struct drm_psb_private *dev_priv =
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(struct drm_psb_private *) dev->dev_private;
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unsigned long irqflags;
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PSB_DEBUG_ENTRY("\n");
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spin_lock_irqsave(&dev_priv->irqmask_lock, irqflags);
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/*This register is safe even if display island is off*/
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PSB_WVDC32(dev_priv->vdc_irq_mask, PSB_INT_ENABLE_R);
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if (hw_islands & OSPM_DISPLAY_ISLAND) {
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if (true/*powermgmt_is_hw_on(dev->pdev, PSB_DISPLAY_ISLAND)*/) {
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PSB_WVDC32(0xFFFFFFFF, PSB_HWSTAM);
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if (dev->vblank_enabled[0])
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psb_enable_pipestat(dev_priv, 0,
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PIPE_VBLANK_INTERRUPT_ENABLE);
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else
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psb_disable_pipestat(dev_priv, 0,
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PIPE_VBLANK_INTERRUPT_ENABLE);
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if (dev->vblank_enabled[1])
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psb_enable_pipestat(dev_priv, 1,
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PIPE_VBLANK_INTERRUPT_ENABLE);
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else
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psb_disable_pipestat(dev_priv, 1,
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PIPE_VBLANK_INTERRUPT_ENABLE);
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if (dev->vblank_enabled[2])
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psb_enable_pipestat(dev_priv, 2,
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PIPE_VBLANK_INTERRUPT_ENABLE);
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else
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psb_disable_pipestat(dev_priv, 2,
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PIPE_VBLANK_INTERRUPT_ENABLE);
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}
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}
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spin_unlock_irqrestore(&dev_priv->irqmask_lock, irqflags);
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return 0;
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}
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void psb_irq_uninstall(struct drm_device *dev)
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{
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psb_irq_uninstall_islands(dev, OSPM_ALL_ISLANDS);
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}
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void psb_irq_uninstall_islands(struct drm_device *dev, int hw_islands)
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{
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struct drm_psb_private *dev_priv =
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(struct drm_psb_private *) dev->dev_private;
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unsigned long irqflags;
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PSB_DEBUG_ENTRY("\n");
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spin_lock_irqsave(&dev_priv->irqmask_lock, irqflags);
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if (hw_islands & OSPM_DISPLAY_ISLAND) {
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if (true/*powermgmt_is_hw_on(dev->pdev, PSB_DISPLAY_ISLAND)*/) {
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PSB_WVDC32(0xFFFFFFFF, PSB_HWSTAM);
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if (dev->vblank_enabled[0])
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psb_disable_pipestat(dev_priv, 0,
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PIPE_VBLANK_INTERRUPT_ENABLE);
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if (dev->vblank_enabled[1])
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psb_disable_pipestat(dev_priv, 1,
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PIPE_VBLANK_INTERRUPT_ENABLE);
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if (dev->vblank_enabled[2])
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psb_disable_pipestat(dev_priv, 2,
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PIPE_VBLANK_INTERRUPT_ENABLE);
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}
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dev_priv->vdc_irq_mask &= _PSB_IRQ_SGX_FLAG |
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_PSB_IRQ_MSVDX_FLAG |
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_LNC_IRQ_TOPAZ_FLAG;
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}
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/*TODO: remove following code*/
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if (hw_islands & OSPM_GRAPHICS_ISLAND)
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dev_priv->vdc_irq_mask &= ~_PSB_IRQ_SGX_FLAG;
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/*These two registers are safe even if display island is off*/
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PSB_WVDC32(~dev_priv->vdc_irq_mask, PSB_INT_MASK_R);
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PSB_WVDC32(dev_priv->vdc_irq_mask, PSB_INT_ENABLE_R);
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wmb();
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/*This register is safe even if display island is off*/
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PSB_WVDC32(PSB_RVDC32(PSB_INT_IDENTITY_R), PSB_INT_IDENTITY_R);
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spin_unlock_irqrestore(&dev_priv->irqmask_lock, irqflags);
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}
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void psb_irq_turn_on_dpst(struct drm_device *dev)
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{
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struct drm_psb_private *dev_priv =
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(struct drm_psb_private *) dev->dev_private;
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u32 hist_reg;
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u32 pwm_reg;
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if (ospm_power_using_hw_begin(OSPM_DISPLAY_ISLAND,
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OSPM_UHB_ONLY_IF_ON)) {
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PSB_WVDC32(1 << 31, HISTOGRAM_LOGIC_CONTROL);
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hist_reg = PSB_RVDC32(HISTOGRAM_LOGIC_CONTROL);
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PSB_WVDC32(1 << 31, HISTOGRAM_INT_CONTROL);
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hist_reg = PSB_RVDC32(HISTOGRAM_INT_CONTROL);
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PSB_WVDC32(0x80010100, PWM_CONTROL_LOGIC);
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pwm_reg = PSB_RVDC32(PWM_CONTROL_LOGIC);
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PSB_WVDC32(pwm_reg | PWM_PHASEIN_ENABLE
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| PWM_PHASEIN_INT_ENABLE,
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PWM_CONTROL_LOGIC);
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pwm_reg = PSB_RVDC32(PWM_CONTROL_LOGIC);
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psb_enable_pipestat(dev_priv, 0, PIPE_DPST_EVENT_ENABLE);
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hist_reg = PSB_RVDC32(HISTOGRAM_INT_CONTROL);
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PSB_WVDC32(hist_reg | HISTOGRAM_INT_CTRL_CLEAR,
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HISTOGRAM_INT_CONTROL);
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pwm_reg = PSB_RVDC32(PWM_CONTROL_LOGIC);
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PSB_WVDC32(pwm_reg | 0x80010100 | PWM_PHASEIN_ENABLE,
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PWM_CONTROL_LOGIC);
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ospm_power_using_hw_end(OSPM_DISPLAY_ISLAND);
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}
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}
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int psb_irq_enable_dpst(struct drm_device *dev)
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{
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struct drm_psb_private *dev_priv =
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(struct drm_psb_private *) dev->dev_private;
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unsigned long irqflags;
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PSB_DEBUG_ENTRY("\n");
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spin_lock_irqsave(&dev_priv->irqmask_lock, irqflags);
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/* enable DPST */
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mid_enable_pipe_event(dev_priv, 0);
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psb_irq_turn_on_dpst(dev);
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spin_unlock_irqrestore(&dev_priv->irqmask_lock, irqflags);
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return 0;
|
|
}
|
|
|
|
void psb_irq_turn_off_dpst(struct drm_device *dev)
|
|
{
|
|
struct drm_psb_private *dev_priv =
|
|
(struct drm_psb_private *) dev->dev_private;
|
|
u32 hist_reg;
|
|
u32 pwm_reg;
|
|
|
|
if (ospm_power_using_hw_begin(OSPM_DISPLAY_ISLAND,
|
|
OSPM_UHB_ONLY_IF_ON)) {
|
|
PSB_WVDC32(0x00000000, HISTOGRAM_INT_CONTROL);
|
|
hist_reg = PSB_RVDC32(HISTOGRAM_INT_CONTROL);
|
|
|
|
psb_disable_pipestat(dev_priv, 0, PIPE_DPST_EVENT_ENABLE);
|
|
|
|
pwm_reg = PSB_RVDC32(PWM_CONTROL_LOGIC);
|
|
PSB_WVDC32(pwm_reg & !(PWM_PHASEIN_INT_ENABLE),
|
|
PWM_CONTROL_LOGIC);
|
|
pwm_reg = PSB_RVDC32(PWM_CONTROL_LOGIC);
|
|
|
|
ospm_power_using_hw_end(OSPM_DISPLAY_ISLAND);
|
|
}
|
|
}
|
|
|
|
int psb_irq_disable_dpst(struct drm_device *dev)
|
|
{
|
|
struct drm_psb_private *dev_priv =
|
|
(struct drm_psb_private *) dev->dev_private;
|
|
unsigned long irqflags;
|
|
|
|
PSB_DEBUG_ENTRY("\n");
|
|
|
|
spin_lock_irqsave(&dev_priv->irqmask_lock, irqflags);
|
|
|
|
mid_disable_pipe_event(dev_priv, 0);
|
|
psb_irq_turn_off_dpst(dev);
|
|
|
|
spin_unlock_irqrestore(&dev_priv->irqmask_lock, irqflags);
|
|
|
|
return 0;
|
|
}
|
|
|
|
#ifdef PSB_FIXME
|
|
static int psb_vblank_do_wait(struct drm_device *dev,
|
|
unsigned int *sequence, atomic_t *counter)
|
|
{
|
|
unsigned int cur_vblank;
|
|
int ret = 0;
|
|
DRM_WAIT_ON(ret, dev->vbl_queue, 3 * DRM_HZ,
|
|
(((cur_vblank = atomic_read(counter))
|
|
- *sequence) <= (1 << 23)));
|
|
*sequence = cur_vblank;
|
|
|
|
return ret;
|
|
}
|
|
#endif
|
|
|
|
/*
|
|
* It is used to enable VBLANK interrupt
|
|
*/
|
|
int psb_enable_vblank(struct drm_device *dev, int pipe)
|
|
{
|
|
struct drm_psb_private *dev_priv =
|
|
(struct drm_psb_private *) dev->dev_private;
|
|
unsigned long irqflags;
|
|
uint32_t reg_val = 0;
|
|
uint32_t pipeconf_reg = mid_pipeconf(pipe);
|
|
|
|
PSB_DEBUG_ENTRY("\n");
|
|
|
|
if (ospm_power_using_hw_begin(OSPM_DISPLAY_ISLAND,
|
|
OSPM_UHB_ONLY_IF_ON)) {
|
|
reg_val = REG_READ(pipeconf_reg);
|
|
ospm_power_using_hw_end(OSPM_DISPLAY_ISLAND);
|
|
}
|
|
|
|
if (!(reg_val & PIPEACONF_ENABLE))
|
|
return -EINVAL;
|
|
|
|
spin_lock_irqsave(&dev_priv->irqmask_lock, irqflags);
|
|
|
|
drm_psb_disable_vsync = 0;
|
|
mid_enable_pipe_event(dev_priv, pipe);
|
|
psb_enable_pipestat(dev_priv, pipe, PIPE_VBLANK_INTERRUPT_ENABLE);
|
|
|
|
spin_unlock_irqrestore(&dev_priv->irqmask_lock, irqflags);
|
|
|
|
return 0;
|
|
}
|
|
|
|
/*
|
|
* It is used to disable VBLANK interrupt
|
|
*/
|
|
void psb_disable_vblank(struct drm_device *dev, int pipe)
|
|
{
|
|
struct drm_psb_private *dev_priv =
|
|
(struct drm_psb_private *) dev->dev_private;
|
|
unsigned long irqflags;
|
|
|
|
PSB_DEBUG_ENTRY("\n");
|
|
|
|
spin_lock_irqsave(&dev_priv->irqmask_lock, irqflags);
|
|
|
|
drm_psb_disable_vsync = 1;
|
|
mid_disable_pipe_event(dev_priv, pipe);
|
|
psb_disable_pipestat(dev_priv, pipe, PIPE_VBLANK_INTERRUPT_ENABLE);
|
|
|
|
spin_unlock_irqrestore(&dev_priv->irqmask_lock, irqflags);
|
|
}
|
|
|
|
/* Called from drm generic code, passed a 'crtc', which
|
|
* we use as a pipe index
|
|
*/
|
|
u32 psb_get_vblank_counter(struct drm_device *dev, int pipe)
|
|
{
|
|
uint32_t high_frame = PIPEAFRAMEHIGH;
|
|
uint32_t low_frame = PIPEAFRAMEPIXEL;
|
|
uint32_t pipeconf_reg = PIPEACONF;
|
|
uint32_t reg_val = 0;
|
|
uint32_t high1 = 0, high2 = 0, low = 0, count = 0;
|
|
|
|
switch (pipe) {
|
|
case 0:
|
|
break;
|
|
case 1:
|
|
high_frame = PIPEBFRAMEHIGH;
|
|
low_frame = PIPEBFRAMEPIXEL;
|
|
pipeconf_reg = PIPEBCONF;
|
|
break;
|
|
case 2:
|
|
high_frame = PIPECFRAMEHIGH;
|
|
low_frame = PIPECFRAMEPIXEL;
|
|
pipeconf_reg = PIPECCONF;
|
|
break;
|
|
default:
|
|
DRM_ERROR("%s, invalded pipe.\n", __func__);
|
|
return 0;
|
|
}
|
|
|
|
if (!ospm_power_using_hw_begin(OSPM_DISPLAY_ISLAND, false))
|
|
return 0;
|
|
|
|
reg_val = REG_READ(pipeconf_reg);
|
|
|
|
if (!(reg_val & PIPEACONF_ENABLE)) {
|
|
DRM_ERROR("trying to get vblank count for disabled pipe %d\n",
|
|
pipe);
|
|
goto psb_get_vblank_counter_exit;
|
|
}
|
|
|
|
/*
|
|
* High & low register fields aren't synchronized, so make sure
|
|
* we get a low value that's stable across two reads of the high
|
|
* register.
|
|
*/
|
|
do {
|
|
high1 = ((REG_READ(high_frame) & PIPE_FRAME_HIGH_MASK) >>
|
|
PIPE_FRAME_HIGH_SHIFT);
|
|
low = ((REG_READ(low_frame) & PIPE_FRAME_LOW_MASK) >>
|
|
PIPE_FRAME_LOW_SHIFT);
|
|
high2 = ((REG_READ(high_frame) & PIPE_FRAME_HIGH_MASK) >>
|
|
PIPE_FRAME_HIGH_SHIFT);
|
|
} while (high1 != high2);
|
|
|
|
count = (high1 << 8) | low;
|
|
|
|
psb_get_vblank_counter_exit:
|
|
|
|
ospm_power_using_hw_end(OSPM_DISPLAY_ISLAND);
|
|
|
|
return count;
|
|
}
|
|
|