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c5d4603961
PCIe controllers in X-Gene SoCs are not ECAM compliant: software needs to configure additional controller's register to address device at bus:dev:function. Add a quirk to discover controller MMIO register space and configure controller registers to select and address the target secondary device. The quirk will only be applied for X-Gene PCIe MCFG table with OEM revison 1, 2, 3 or 4 (PCIe controller v1 and v2 on X-Gene SoCs). Tested-by: Jon Masters <jcm@redhat.com> Signed-off-by: Duc Dang <dhdang@apm.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
76 lines
2.5 KiB
C
76 lines
2.5 KiB
C
/*
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* Copyright 2016 Broadcom
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License, version 2, as
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* published by the Free Software Foundation (the "GPL").
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License version 2 (GPLv2) for more details.
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*
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* You should have received a copy of the GNU General Public License
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* version 2 (GPLv2) along with this source code.
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*/
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#ifndef DRIVERS_PCI_ECAM_H
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#define DRIVERS_PCI_ECAM_H
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#include <linux/kernel.h>
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#include <linux/platform_device.h>
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/*
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* struct to hold pci ops and bus shift of the config window
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* for a PCI controller.
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*/
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struct pci_config_window;
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struct pci_ecam_ops {
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unsigned int bus_shift;
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struct pci_ops pci_ops;
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int (*init)(struct pci_config_window *);
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};
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/*
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* struct to hold the mappings of a config space window. This
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* is expected to be used as sysdata for PCI controllers that
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* use ECAM.
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*/
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struct pci_config_window {
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struct resource res;
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struct resource busr;
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void *priv;
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struct pci_ecam_ops *ops;
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union {
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void __iomem *win; /* 64-bit single mapping */
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void __iomem **winp; /* 32-bit per-bus mapping */
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};
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struct device *parent;/* ECAM res was from this dev */
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};
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/* create and free pci_config_window */
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struct pci_config_window *pci_ecam_create(struct device *dev,
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struct resource *cfgres, struct resource *busr,
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struct pci_ecam_ops *ops);
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void pci_ecam_free(struct pci_config_window *cfg);
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/* map_bus when ->sysdata is an instance of pci_config_window */
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void __iomem *pci_ecam_map_bus(struct pci_bus *bus, unsigned int devfn,
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int where);
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/* default ECAM ops */
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extern struct pci_ecam_ops pci_generic_ecam_ops;
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#if defined(CONFIG_ACPI) && defined(CONFIG_PCI_QUIRKS)
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extern struct pci_ecam_ops pci_32b_ops; /* 32-bit accesses only */
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extern struct pci_ecam_ops hisi_pcie_ops; /* HiSilicon */
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extern struct pci_ecam_ops thunder_pem_ecam_ops; /* Cavium ThunderX 1.x & 2.x */
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extern struct pci_ecam_ops pci_thunder_ecam_ops; /* Cavium ThunderX 1.x */
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extern struct pci_ecam_ops xgene_v1_pcie_ecam_ops; /* APM X-Gene PCIe v1 */
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extern struct pci_ecam_ops xgene_v2_pcie_ecam_ops; /* APM X-Gene PCIe v2.x */
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#endif
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#ifdef CONFIG_PCI_HOST_GENERIC
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/* for DT-based PCI controllers that support ECAM */
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int pci_host_common_probe(struct platform_device *pdev,
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struct pci_ecam_ops *ops);
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#endif
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#endif
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