127 lines
3.0 KiB
YAML
127 lines
3.0 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/display/renesas,rzg2l-du.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Renesas RZ/G2L Display Unit (DU)
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maintainers:
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- Biju Das <biju.das.jz@bp.renesas.com>
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- Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
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description: |
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These DT bindings describe the Display Unit embedded in the Renesas RZ/G2L
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and RZ/V2L SoCs.
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properties:
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compatible:
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oneOf:
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- enum:
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- renesas,r9a07g044-du # RZ/G2{L,LC}
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- items:
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- enum:
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- renesas,r9a07g054-du # RZ/V2L
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- const: renesas,r9a07g044-du # RZ/G2L fallback
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reg:
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maxItems: 1
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interrupts:
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maxItems: 1
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clocks:
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items:
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- description: Main clock
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- description: Register access clock
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- description: Video clock
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clock-names:
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items:
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- const: aclk
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- const: pclk
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- const: vclk
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resets:
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maxItems: 1
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power-domains:
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maxItems: 1
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ports:
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$ref: /schemas/graph.yaml#/properties/ports
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description: |
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The connections to the DU output video ports are modeled using the OF
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graph bindings. The number of ports and their assignment are
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model-dependent. Each port shall have a single endpoint.
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patternProperties:
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"^port@[0-1]$":
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$ref: /schemas/graph.yaml#/properties/port
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unevaluatedProperties: false
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required:
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- port@0
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unevaluatedProperties: false
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renesas,vsps:
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$ref: /schemas/types.yaml#/definitions/phandle-array
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items:
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items:
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- description: phandle to VSP instance that serves the DU channel
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- description: Channel index identifying the LIF instance in that VSP
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description:
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A list of phandle and channel index tuples to the VSPs that handle the
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memory interfaces for the DU channels.
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required:
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- compatible
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- reg
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- interrupts
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- clocks
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- clock-names
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- resets
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- power-domains
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- ports
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- renesas,vsps
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additionalProperties: false
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examples:
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# RZ/G2L DU
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- |
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#include <dt-bindings/clock/r9a07g044-cpg.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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display@10890000 {
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compatible = "renesas,r9a07g044-du";
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reg = <0x10890000 0x10000>;
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interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg CPG_MOD R9A07G044_LCDC_CLK_A>,
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<&cpg CPG_MOD R9A07G044_LCDC_CLK_P>,
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<&cpg CPG_MOD R9A07G044_LCDC_CLK_D>;
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clock-names = "aclk", "pclk", "vclk";
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resets = <&cpg R9A07G044_LCDC_RESET_N>;
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power-domains = <&cpg>;
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renesas,vsps = <&vspd0 0>;
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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endpoint {
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remote-endpoint = <&dsi0_in>;
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};
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};
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port@1 {
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reg = <1>;
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};
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};
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};
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...
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