423 lines
11 KiB
C
423 lines
11 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* RZ/G2L Display Unit CRTCs
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*
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* Copyright (C) 2023 Renesas Electronics Corporation
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*
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* Based on rcar_du_crtc.c
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*/
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#include <linux/clk.h>
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#include <linux/mutex.h>
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#include <linux/platform_device.h>
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#include <linux/reset.h>
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#include <drm/drm_atomic.h>
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#include <drm/drm_atomic_helper.h>
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#include <drm/drm_bridge.h>
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#include <drm/drm_crtc.h>
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#include <drm/drm_device.h>
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#include <drm/drm_framebuffer.h>
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#include <drm/drm_gem_dma_helper.h>
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#include <drm/drm_vblank.h>
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#include "rzg2l_du_crtc.h"
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#include "rzg2l_du_drv.h"
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#include "rzg2l_du_encoder.h"
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#include "rzg2l_du_kms.h"
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#include "rzg2l_du_vsp.h"
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#define DU_MCR0 0x00
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#define DU_MCR0_DI_EN BIT(8)
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#define DU_DITR0 0x10
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#define DU_DITR0_DEMD_HIGH (BIT(8) | BIT(9))
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#define DU_DITR0_VSPOL BIT(16)
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#define DU_DITR0_HSPOL BIT(17)
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#define DU_DITR1 0x14
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#define DU_DITR1_VSA(x) ((x) << 0)
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#define DU_DITR1_VACTIVE(x) ((x) << 16)
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#define DU_DITR2 0x18
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#define DU_DITR2_VBP(x) ((x) << 0)
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#define DU_DITR2_VFP(x) ((x) << 16)
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#define DU_DITR3 0x1c
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#define DU_DITR3_HSA(x) ((x) << 0)
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#define DU_DITR3_HACTIVE(x) ((x) << 16)
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#define DU_DITR4 0x20
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#define DU_DITR4_HBP(x) ((x) << 0)
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#define DU_DITR4_HFP(x) ((x) << 16)
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#define DU_MCR1 0x40
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#define DU_MCR1_PB_AUTOCLR BIT(16)
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#define DU_PBCR0 0x4c
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#define DU_PBCR0_PB_DEP(x) ((x) << 0)
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/* -----------------------------------------------------------------------------
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* Hardware Setup
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*/
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static void rzg2l_du_crtc_set_display_timing(struct rzg2l_du_crtc *rcrtc)
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{
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const struct drm_display_mode *mode = &rcrtc->crtc.state->adjusted_mode;
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unsigned long mode_clock = mode->clock * 1000;
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u32 ditr0, ditr1, ditr2, ditr3, ditr4, pbcr0;
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struct rzg2l_du_device *rcdu = rcrtc->dev;
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clk_prepare_enable(rcrtc->rzg2l_clocks.dclk);
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clk_set_rate(rcrtc->rzg2l_clocks.dclk, mode_clock);
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ditr0 = (DU_DITR0_DEMD_HIGH
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| ((mode->flags & DRM_MODE_FLAG_PVSYNC) ? DU_DITR0_VSPOL : 0)
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| ((mode->flags & DRM_MODE_FLAG_PHSYNC) ? DU_DITR0_HSPOL : 0));
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ditr1 = DU_DITR1_VSA(mode->vsync_end - mode->vsync_start)
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| DU_DITR1_VACTIVE(mode->vdisplay);
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ditr2 = DU_DITR2_VBP(mode->vtotal - mode->vsync_end)
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| DU_DITR2_VFP(mode->vsync_start - mode->vdisplay);
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ditr3 = DU_DITR3_HSA(mode->hsync_end - mode->hsync_start)
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| DU_DITR3_HACTIVE(mode->hdisplay);
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ditr4 = DU_DITR4_HBP(mode->htotal - mode->hsync_end)
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| DU_DITR4_HFP(mode->hsync_start - mode->hdisplay);
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pbcr0 = DU_PBCR0_PB_DEP(0x1f);
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writel(ditr0, rcdu->mmio + DU_DITR0);
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writel(ditr1, rcdu->mmio + DU_DITR1);
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writel(ditr2, rcdu->mmio + DU_DITR2);
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writel(ditr3, rcdu->mmio + DU_DITR3);
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writel(ditr4, rcdu->mmio + DU_DITR4);
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writel(pbcr0, rcdu->mmio + DU_PBCR0);
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/* Enable auto clear */
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writel(DU_MCR1_PB_AUTOCLR, rcdu->mmio + DU_MCR1);
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}
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/* -----------------------------------------------------------------------------
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* Page Flip
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*/
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void rzg2l_du_crtc_finish_page_flip(struct rzg2l_du_crtc *rcrtc)
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{
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struct drm_pending_vblank_event *event;
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struct drm_device *dev = rcrtc->crtc.dev;
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unsigned long flags;
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spin_lock_irqsave(&dev->event_lock, flags);
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event = rcrtc->event;
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rcrtc->event = NULL;
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spin_unlock_irqrestore(&dev->event_lock, flags);
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if (!event)
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return;
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spin_lock_irqsave(&dev->event_lock, flags);
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drm_crtc_send_vblank_event(&rcrtc->crtc, event);
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wake_up(&rcrtc->flip_wait);
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spin_unlock_irqrestore(&dev->event_lock, flags);
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drm_crtc_vblank_put(&rcrtc->crtc);
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}
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static bool rzg2l_du_crtc_page_flip_pending(struct rzg2l_du_crtc *rcrtc)
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{
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struct drm_device *dev = rcrtc->crtc.dev;
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unsigned long flags;
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bool pending;
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spin_lock_irqsave(&dev->event_lock, flags);
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pending = rcrtc->event;
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spin_unlock_irqrestore(&dev->event_lock, flags);
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return pending;
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}
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static void rzg2l_du_crtc_wait_page_flip(struct rzg2l_du_crtc *rcrtc)
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{
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struct rzg2l_du_device *rcdu = rcrtc->dev;
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if (wait_event_timeout(rcrtc->flip_wait,
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!rzg2l_du_crtc_page_flip_pending(rcrtc),
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msecs_to_jiffies(50)))
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return;
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dev_warn(rcdu->dev, "page flip timeout\n");
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rzg2l_du_crtc_finish_page_flip(rcrtc);
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}
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/* -----------------------------------------------------------------------------
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* Start/Stop and Suspend/Resume
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*/
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static void rzg2l_du_crtc_setup(struct rzg2l_du_crtc *rcrtc)
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{
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/* Configure display timings and output routing */
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rzg2l_du_crtc_set_display_timing(rcrtc);
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/* Enable the VSP compositor. */
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rzg2l_du_vsp_enable(rcrtc);
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/* Turn vertical blanking interrupt reporting on. */
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drm_crtc_vblank_on(&rcrtc->crtc);
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}
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static int rzg2l_du_crtc_get(struct rzg2l_du_crtc *rcrtc)
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{
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int ret;
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/*
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* Guard against double-get, as the function is called from both the
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* .atomic_enable() and .atomic_flush() handlers.
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*/
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if (rcrtc->initialized)
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return 0;
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ret = clk_prepare_enable(rcrtc->rzg2l_clocks.aclk);
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if (ret < 0)
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return ret;
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ret = clk_prepare_enable(rcrtc->rzg2l_clocks.pclk);
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if (ret < 0)
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goto error_bus_clock;
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ret = reset_control_deassert(rcrtc->rstc);
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if (ret < 0)
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goto error_peri_clock;
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rzg2l_du_crtc_setup(rcrtc);
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rcrtc->initialized = true;
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return 0;
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error_peri_clock:
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clk_disable_unprepare(rcrtc->rzg2l_clocks.pclk);
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error_bus_clock:
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clk_disable_unprepare(rcrtc->rzg2l_clocks.aclk);
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return ret;
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}
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static void rzg2l_du_crtc_put(struct rzg2l_du_crtc *rcrtc)
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{
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clk_disable_unprepare(rcrtc->rzg2l_clocks.dclk);
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reset_control_assert(rcrtc->rstc);
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clk_disable_unprepare(rcrtc->rzg2l_clocks.pclk);
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clk_disable_unprepare(rcrtc->rzg2l_clocks.aclk);
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rcrtc->initialized = false;
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}
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static void rzg2l_du_start_stop(struct rzg2l_du_crtc *rcrtc, bool start)
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{
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struct rzg2l_du_device *rcdu = rcrtc->dev;
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writel(start ? DU_MCR0_DI_EN : 0, rcdu->mmio + DU_MCR0);
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}
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static void rzg2l_du_crtc_start(struct rzg2l_du_crtc *rcrtc)
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{
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rzg2l_du_start_stop(rcrtc, true);
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}
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static void rzg2l_du_crtc_stop(struct rzg2l_du_crtc *rcrtc)
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{
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struct drm_crtc *crtc = &rcrtc->crtc;
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/*
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* Disable vertical blanking interrupt reporting. We first need to wait
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* for page flip completion before stopping the CRTC as userspace
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* expects page flips to eventually complete.
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*/
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rzg2l_du_crtc_wait_page_flip(rcrtc);
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drm_crtc_vblank_off(crtc);
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/* Disable the VSP compositor. */
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rzg2l_du_vsp_disable(rcrtc);
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rzg2l_du_start_stop(rcrtc, false);
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}
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/* -----------------------------------------------------------------------------
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* CRTC Functions
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*/
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static void rzg2l_du_crtc_atomic_enable(struct drm_crtc *crtc,
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struct drm_atomic_state *state)
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{
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struct rzg2l_du_crtc *rcrtc = to_rzg2l_crtc(crtc);
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rzg2l_du_crtc_get(rcrtc);
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rzg2l_du_crtc_start(rcrtc);
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}
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static void rzg2l_du_crtc_atomic_disable(struct drm_crtc *crtc,
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struct drm_atomic_state *state)
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{
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struct rzg2l_du_crtc *rcrtc = to_rzg2l_crtc(crtc);
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rzg2l_du_crtc_stop(rcrtc);
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rzg2l_du_crtc_put(rcrtc);
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spin_lock_irq(&crtc->dev->event_lock);
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if (crtc->state->event) {
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drm_crtc_send_vblank_event(crtc, crtc->state->event);
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crtc->state->event = NULL;
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}
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spin_unlock_irq(&crtc->dev->event_lock);
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}
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static void rzg2l_du_crtc_atomic_flush(struct drm_crtc *crtc,
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struct drm_atomic_state *state)
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{
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struct rzg2l_du_crtc *rcrtc = to_rzg2l_crtc(crtc);
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struct drm_device *dev = rcrtc->crtc.dev;
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unsigned long flags;
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WARN_ON(!crtc->state->enable);
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if (crtc->state->event) {
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WARN_ON(drm_crtc_vblank_get(crtc) != 0);
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spin_lock_irqsave(&dev->event_lock, flags);
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rcrtc->event = crtc->state->event;
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crtc->state->event = NULL;
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spin_unlock_irqrestore(&dev->event_lock, flags);
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}
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rzg2l_du_vsp_atomic_flush(rcrtc);
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}
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static const struct drm_crtc_helper_funcs crtc_helper_funcs = {
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.atomic_flush = rzg2l_du_crtc_atomic_flush,
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.atomic_enable = rzg2l_du_crtc_atomic_enable,
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.atomic_disable = rzg2l_du_crtc_atomic_disable,
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};
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static struct drm_crtc_state *
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rzg2l_du_crtc_atomic_duplicate_state(struct drm_crtc *crtc)
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{
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struct rzg2l_du_crtc_state *state;
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struct rzg2l_du_crtc_state *copy;
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if (WARN_ON(!crtc->state))
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return NULL;
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state = to_rzg2l_crtc_state(crtc->state);
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copy = kmemdup(state, sizeof(*state), GFP_KERNEL);
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if (!copy)
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return NULL;
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__drm_atomic_helper_crtc_duplicate_state(crtc, ©->state);
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return ©->state;
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}
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static void rzg2l_du_crtc_atomic_destroy_state(struct drm_crtc *crtc,
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struct drm_crtc_state *state)
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{
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__drm_atomic_helper_crtc_destroy_state(state);
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kfree(to_rzg2l_crtc_state(state));
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}
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static void rzg2l_du_crtc_reset(struct drm_crtc *crtc)
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{
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struct rzg2l_du_crtc_state *state;
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if (crtc->state) {
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rzg2l_du_crtc_atomic_destroy_state(crtc, crtc->state);
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crtc->state = NULL;
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}
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state = kzalloc(sizeof(*state), GFP_KERNEL);
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if (!state)
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return;
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__drm_atomic_helper_crtc_reset(crtc, &state->state);
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}
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static int rzg2l_du_crtc_enable_vblank(struct drm_crtc *crtc)
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{
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struct rzg2l_du_crtc *rcrtc = to_rzg2l_crtc(crtc);
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rcrtc->vblank_enable = true;
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return 0;
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}
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static void rzg2l_du_crtc_disable_vblank(struct drm_crtc *crtc)
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{
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struct rzg2l_du_crtc *rcrtc = to_rzg2l_crtc(crtc);
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rcrtc->vblank_enable = false;
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}
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static const struct drm_crtc_funcs crtc_funcs_rz = {
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.reset = rzg2l_du_crtc_reset,
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.set_config = drm_atomic_helper_set_config,
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.page_flip = drm_atomic_helper_page_flip,
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.atomic_duplicate_state = rzg2l_du_crtc_atomic_duplicate_state,
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.atomic_destroy_state = rzg2l_du_crtc_atomic_destroy_state,
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.enable_vblank = rzg2l_du_crtc_enable_vblank,
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.disable_vblank = rzg2l_du_crtc_disable_vblank,
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};
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/* -----------------------------------------------------------------------------
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* Initialization
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*/
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int rzg2l_du_crtc_create(struct rzg2l_du_device *rcdu)
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{
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struct rzg2l_du_crtc *rcrtc = &rcdu->crtcs[0];
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struct drm_crtc *crtc = &rcrtc->crtc;
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struct drm_plane *primary;
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int ret;
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rcrtc->rstc = devm_reset_control_get_shared(rcdu->dev, NULL);
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if (IS_ERR(rcrtc->rstc)) {
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dev_err(rcdu->dev, "can't get cpg reset\n");
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return PTR_ERR(rcrtc->rstc);
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}
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rcrtc->rzg2l_clocks.aclk = devm_clk_get(rcdu->dev, "aclk");
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if (IS_ERR(rcrtc->rzg2l_clocks.aclk)) {
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dev_err(rcdu->dev, "no axi clock for DU\n");
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return PTR_ERR(rcrtc->rzg2l_clocks.aclk);
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}
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rcrtc->rzg2l_clocks.pclk = devm_clk_get(rcdu->dev, "pclk");
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if (IS_ERR(rcrtc->rzg2l_clocks.pclk)) {
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dev_err(rcdu->dev, "no peripheral clock for DU\n");
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return PTR_ERR(rcrtc->rzg2l_clocks.pclk);
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}
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rcrtc->rzg2l_clocks.dclk = devm_clk_get(rcdu->dev, "vclk");
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if (IS_ERR(rcrtc->rzg2l_clocks.dclk)) {
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dev_err(rcdu->dev, "no video clock for DU\n");
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return PTR_ERR(rcrtc->rzg2l_clocks.dclk);
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}
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init_waitqueue_head(&rcrtc->flip_wait);
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rcrtc->dev = rcdu;
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primary = rzg2l_du_vsp_get_drm_plane(rcrtc, rcrtc->vsp_pipe);
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if (IS_ERR(primary))
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return PTR_ERR(primary);
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ret = drmm_crtc_init_with_planes(&rcdu->ddev, crtc, primary, NULL,
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&crtc_funcs_rz, NULL);
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if (ret < 0)
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return ret;
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drm_crtc_helper_add(crtc, &crtc_helper_funcs);
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return 0;
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}
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