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efeff7b38e
The way exec ufences are coded only 1 ufence per IOCTL will be signaled. It is possible to fix this but for current use cases 1 ufence per IOCTL is sufficient. Enforce a limit of 1 ufence per IOCTL (both exec and bind to be uniform). v2: - Add fixes tag (Thomas) Fixes:dd08ebf6c3("drm/xe: Introduce a new DRM driver for Intel GPUs") Cc: Mika Kahola <mika.kahola@intel.com> Cc: Thomas Hellström <thomas.hellstrom@linux.intel.com> Signed-off-by: Matthew Brost <matthew.brost@intel.com> Reviewed-by: Brian Welty <brian.welty@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240124234413.1640825-1-matthew.brost@intel.com (cherry picked from commitd1df9bfbf6) Signed-off-by: Thomas Hellström <thomas.hellstrom@linux.intel.com>
41 lines
1.1 KiB
C
41 lines
1.1 KiB
C
/* SPDX-License-Identifier: MIT */
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/*
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* Copyright © 2021 Intel Corporation
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*/
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#ifndef _XE_SYNC_H_
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#define _XE_SYNC_H_
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#include "xe_sync_types.h"
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struct xe_device;
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struct xe_exec_queue;
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struct xe_file;
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struct xe_sched_job;
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struct xe_vm;
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#define SYNC_PARSE_FLAG_EXEC BIT(0)
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#define SYNC_PARSE_FLAG_LR_MODE BIT(1)
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#define SYNC_PARSE_FLAG_DISALLOW_USER_FENCE BIT(2)
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int xe_sync_entry_parse(struct xe_device *xe, struct xe_file *xef,
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struct xe_sync_entry *sync,
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struct drm_xe_sync __user *sync_user,
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unsigned int flags);
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int xe_sync_entry_wait(struct xe_sync_entry *sync);
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int xe_sync_entry_add_deps(struct xe_sync_entry *sync,
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struct xe_sched_job *job);
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void xe_sync_entry_signal(struct xe_sync_entry *sync,
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struct xe_sched_job *job,
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struct dma_fence *fence);
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void xe_sync_entry_cleanup(struct xe_sync_entry *sync);
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struct dma_fence *
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xe_sync_in_fence_get(struct xe_sync_entry *sync, int num_sync,
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struct xe_exec_queue *q, struct xe_vm *vm);
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static inline bool xe_sync_is_ufence(struct xe_sync_entry *sync)
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{
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return !!sync->ufence;
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}
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#endif
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