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6ba9cdc096
Provision for multiple Rx/Tx queues. Max of 8 WQs and 8 RQs. Max for completion queue is 8+8=16 and max for interrupt resources is 8+8+2. Add driver/firmware interface for setting up RSS secret key and indirection table. Signed-off-by: Scott Feldman <scofeldm@cisco.com> Signed-off-by: David S. Miller <davem@davemloft.net>
122 lines
3.2 KiB
C
122 lines
3.2 KiB
C
/*
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* Copyright 2008 Cisco Systems, Inc. All rights reserved.
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* Copyright 2007 Nuova Systems, Inc. All rights reserved.
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*
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* This program is free software; you may redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*
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*/
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#ifndef _ENIC_H_
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#define _ENIC_H_
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#include <linux/inet_lro.h>
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#include "vnic_enet.h"
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#include "vnic_dev.h"
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#include "vnic_wq.h"
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#include "vnic_rq.h"
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#include "vnic_cq.h"
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#include "vnic_intr.h"
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#include "vnic_stats.h"
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#include "vnic_nic.h"
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#include "vnic_rss.h"
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#define DRV_NAME "enic"
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#define DRV_DESCRIPTION "Cisco 10G Ethernet Driver"
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#define DRV_VERSION "1.1.0.100"
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#define DRV_COPYRIGHT "Copyright 2008-2009 Cisco Systems, Inc"
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#define PFX DRV_NAME ": "
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#define ENIC_LRO_MAX_DESC 8
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#define ENIC_LRO_MAX_AGGR 64
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#define ENIC_BARS_MAX 6
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#define ENIC_WQ_MAX 8
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#define ENIC_RQ_MAX 8
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#define ENIC_CQ_MAX (ENIC_WQ_MAX + ENIC_RQ_MAX)
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#define ENIC_INTR_MAX (ENIC_CQ_MAX + 2)
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enum enic_cq_index {
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ENIC_CQ_RQ,
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ENIC_CQ_WQ,
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};
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enum enic_intx_intr_index {
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ENIC_INTX_WQ_RQ,
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ENIC_INTX_ERR,
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ENIC_INTX_NOTIFY,
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};
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enum enic_msix_intr_index {
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ENIC_MSIX_RQ,
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ENIC_MSIX_WQ,
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ENIC_MSIX_ERR,
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ENIC_MSIX_NOTIFY,
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ENIC_MSIX_MAX,
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};
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struct enic_msix_entry {
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int requested;
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char devname[IFNAMSIZ];
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irqreturn_t (*isr)(int, void *);
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void *devid;
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};
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/* Per-instance private data structure */
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struct enic {
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struct net_device *netdev;
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struct pci_dev *pdev;
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struct vnic_enet_config config;
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struct vnic_dev_bar bar[ENIC_BARS_MAX];
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struct vnic_dev *vdev;
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struct timer_list notify_timer;
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struct work_struct reset;
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struct msix_entry msix_entry[ENIC_MSIX_MAX];
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struct enic_msix_entry msix[ENIC_MSIX_MAX];
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u32 msg_enable;
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spinlock_t devcmd_lock;
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u8 mac_addr[ETH_ALEN];
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u8 mc_addr[ENIC_MULTICAST_PERFECT_FILTERS][ETH_ALEN];
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unsigned int mc_count;
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int csum_rx_enabled;
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u32 port_mtu;
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/* work queue cache line section */
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____cacheline_aligned struct vnic_wq wq[ENIC_WQ_MAX];
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spinlock_t wq_lock[ENIC_WQ_MAX];
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unsigned int wq_count;
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struct vlan_group *vlan_group;
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/* receive queue cache line section */
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____cacheline_aligned struct vnic_rq rq[ENIC_RQ_MAX];
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unsigned int rq_count;
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int (*rq_alloc_buf)(struct vnic_rq *rq);
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u64 rq_truncated_pkts;
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u64 rq_bad_fcs;
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struct napi_struct napi;
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struct net_lro_mgr lro_mgr;
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struct net_lro_desc lro_desc[ENIC_LRO_MAX_DESC];
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/* interrupt resource cache line section */
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____cacheline_aligned struct vnic_intr intr[ENIC_INTR_MAX];
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unsigned int intr_count;
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u32 __iomem *legacy_pba; /* memory-mapped */
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/* completion queue cache line section */
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____cacheline_aligned struct vnic_cq cq[ENIC_CQ_MAX];
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unsigned int cq_count;
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};
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#endif /* _ENIC_H_ */
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