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9d50094dfe
Add a dtsi file for MT7620A SoC and a sample dts file. Signed-off-by: John Crispin <blogic@openwrt.org> Acked-by: Grant Likely <grant.likely@secretlab.ca> Patchwork: http://patchwork.linux-mips.org/patch/5190/
58 lines
1 KiB
Text
58 lines
1 KiB
Text
/ {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "ralink,mtk7620a-soc";
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cpus {
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cpu@0 {
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compatible = "mips,mips24KEc";
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};
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};
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cpuintc: cpuintc@0 {
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#address-cells = <0>;
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#interrupt-cells = <1>;
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interrupt-controller;
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compatible = "mti,cpu-interrupt-controller";
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};
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palmbus@10000000 {
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compatible = "palmbus";
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reg = <0x10000000 0x200000>;
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ranges = <0x0 0x10000000 0x1FFFFF>;
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#address-cells = <1>;
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#size-cells = <1>;
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sysc@0 {
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compatible = "ralink,mt7620a-sysc";
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reg = <0x0 0x100>;
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};
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intc: intc@200 {
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compatible = "ralink,mt7620a-intc", "ralink,rt2880-intc";
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reg = <0x200 0x100>;
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interrupt-controller;
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#interrupt-cells = <1>;
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interrupt-parent = <&cpuintc>;
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interrupts = <2>;
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};
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memc@300 {
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compatible = "ralink,mt7620a-memc", "ralink,rt3050-memc";
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reg = <0x300 0x100>;
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};
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uartlite@c00 {
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compatible = "ralink,mt7620a-uart", "ralink,rt2880-uart", "ns16550a";
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reg = <0xc00 0x100>;
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interrupt-parent = <&intc>;
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interrupts = <12>;
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reg-shift = <2>;
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};
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};
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};
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