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https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
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621b195515
This change adds support for a new "super" bit in the PTE, using the new arch_make_huge_pte() method. The Tilera hypervisor sees the bit set at a given level of the page table and gangs together 4, 16, or 64 consecutive pages from that level of the hierarchy to create a larger TLB entry. One extra "super" page size can be specified at each of the three levels of the page table hierarchy on tilegx, using the "hugepagesz" argument on the boot command line. A new hypervisor API is added to allow Linux to tell the hypervisor how many PTEs to gang together at each level of the page table. To allow pre-allocating huge pages larger than the buddy allocator can handle, this change modifies the Tilera bootmem support to put all of memory on tilegx platforms into bootmem. As part of this change I eliminate the vestigial CONFIG_HIGHPTE support, which never worked anyway, and eliminate the hv_page_size() API in favor of the standard vma_kernel_pagesize() API. Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
98 lines
2.8 KiB
C
98 lines
2.8 KiB
C
/*
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* Copyright 2010 Tilera Corporation. All Rights Reserved.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation, version 2.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
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* NON INFRINGEMENT. See the GNU General Public License for
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* more details.
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*
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*/
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#include <linux/cpumask.h>
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#include <linux/module.h>
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#include <linux/hugetlb.h>
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#include <asm/tlbflush.h>
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#include <asm/homecache.h>
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#include <hv/hypervisor.h>
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/* From tlbflush.h */
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DEFINE_PER_CPU(int, current_asid);
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int min_asid, max_asid;
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/*
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* Note that we flush the L1I (for VM_EXEC pages) as well as the TLB
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* so that when we are unmapping an executable page, we also flush it.
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* Combined with flushing the L1I at context switch time, this means
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* we don't have to do any other icache flushes.
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*/
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void flush_tlb_mm(struct mm_struct *mm)
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{
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HV_Remote_ASID asids[NR_CPUS];
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int i = 0, cpu;
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for_each_cpu(cpu, mm_cpumask(mm)) {
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HV_Remote_ASID *asid = &asids[i++];
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asid->y = cpu / smp_topology.width;
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asid->x = cpu % smp_topology.width;
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asid->asid = per_cpu(current_asid, cpu);
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}
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flush_remote(0, HV_FLUSH_EVICT_L1I, mm_cpumask(mm),
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0, 0, 0, NULL, asids, i);
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}
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void flush_tlb_current_task(void)
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{
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flush_tlb_mm(current->mm);
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}
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void flush_tlb_page_mm(struct vm_area_struct *vma, struct mm_struct *mm,
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unsigned long va)
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{
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unsigned long size = vma_kernel_pagesize(vma);
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int cache = (vma->vm_flags & VM_EXEC) ? HV_FLUSH_EVICT_L1I : 0;
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flush_remote(0, cache, mm_cpumask(mm),
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va, size, size, mm_cpumask(mm), NULL, 0);
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}
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void flush_tlb_page(struct vm_area_struct *vma, unsigned long va)
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{
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flush_tlb_page_mm(vma, vma->vm_mm, va);
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}
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EXPORT_SYMBOL(flush_tlb_page);
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void flush_tlb_range(struct vm_area_struct *vma,
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unsigned long start, unsigned long end)
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{
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unsigned long size = vma_kernel_pagesize(vma);
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struct mm_struct *mm = vma->vm_mm;
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int cache = (vma->vm_flags & VM_EXEC) ? HV_FLUSH_EVICT_L1I : 0;
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flush_remote(0, cache, mm_cpumask(mm), start, end - start, size,
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mm_cpumask(mm), NULL, 0);
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}
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void flush_tlb_all(void)
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{
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int i;
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for (i = 0; ; ++i) {
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HV_VirtAddrRange r = hv_inquire_virtual(i);
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if (r.size == 0)
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break;
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flush_remote(0, HV_FLUSH_EVICT_L1I, cpu_online_mask,
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r.start, r.size, PAGE_SIZE, cpu_online_mask,
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NULL, 0);
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flush_remote(0, 0, NULL,
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r.start, r.size, HPAGE_SIZE, cpu_online_mask,
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NULL, 0);
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}
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}
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void flush_tlb_kernel_range(unsigned long start, unsigned long end)
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{
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flush_remote(0, HV_FLUSH_EVICT_L1I, cpu_online_mask,
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start, end - start, PAGE_SIZE, cpu_online_mask, NULL, 0);
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}
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