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44377f622e
The defines and typedefs (hw_interrupt_type, no_irq_type, irq_desc_t) have been kept around for migration reasons. After more than two years it's time to remove them finally. This patch cleans up one of the remaining users. When all such patches hit mainline we can remove the defines and typedefs finally. Impact: cleanup Convert the last remaining users to struct irq_chip and remove the define. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Cc: Richard Henderson <rth@twiddle.net> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
220 lines
5.3 KiB
C
220 lines
5.3 KiB
C
/*
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* linux/arch/alpha/kernel/sys_rx164.c
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*
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* Copyright (C) 1995 David A Rusling
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* Copyright (C) 1996 Jay A Estabrook
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* Copyright (C) 1998, 1999 Richard Henderson
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*
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* Code supporting the RX164 (PCA56+POLARIS).
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*/
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#include <linux/kernel.h>
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#include <linux/types.h>
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#include <linux/mm.h>
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#include <linux/sched.h>
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#include <linux/pci.h>
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#include <linux/init.h>
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#include <linux/bitops.h>
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#include <asm/ptrace.h>
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#include <asm/system.h>
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#include <asm/dma.h>
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#include <asm/irq.h>
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#include <asm/mmu_context.h>
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#include <asm/io.h>
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#include <asm/pgtable.h>
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#include <asm/core_polaris.h>
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#include <asm/tlbflush.h>
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#include "proto.h"
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#include "irq_impl.h"
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#include "pci_impl.h"
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#include "machvec_impl.h"
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/* Note mask bit is true for ENABLED irqs. */
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static unsigned long cached_irq_mask;
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static inline void
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rx164_update_irq_hw(unsigned long mask)
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{
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volatile unsigned int *irq_mask;
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irq_mask = (void *)(POLARIS_DENSE_CONFIG_BASE + 0x74);
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*irq_mask = mask;
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mb();
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*irq_mask;
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}
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static inline void
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rx164_enable_irq(unsigned int irq)
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{
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rx164_update_irq_hw(cached_irq_mask |= 1UL << (irq - 16));
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}
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static void
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rx164_disable_irq(unsigned int irq)
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{
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rx164_update_irq_hw(cached_irq_mask &= ~(1UL << (irq - 16)));
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}
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static unsigned int
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rx164_startup_irq(unsigned int irq)
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{
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rx164_enable_irq(irq);
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return 0;
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}
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static void
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rx164_end_irq(unsigned int irq)
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{
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if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
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rx164_enable_irq(irq);
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}
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static struct irq_chip rx164_irq_type = {
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.typename = "RX164",
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.startup = rx164_startup_irq,
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.shutdown = rx164_disable_irq,
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.enable = rx164_enable_irq,
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.disable = rx164_disable_irq,
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.ack = rx164_disable_irq,
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.end = rx164_end_irq,
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};
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static void
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rx164_device_interrupt(unsigned long vector)
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{
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unsigned long pld;
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volatile unsigned int *dirr;
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long i;
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/* Read the interrupt summary register. On Polaris, this is
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the DIRR register in PCI config space (offset 0x84). */
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dirr = (void *)(POLARIS_DENSE_CONFIG_BASE + 0x84);
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pld = *dirr;
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/*
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* Now for every possible bit set, work through them and call
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* the appropriate interrupt handler.
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*/
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while (pld) {
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i = ffz(~pld);
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pld &= pld - 1; /* clear least bit set */
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if (i == 20) {
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isa_no_iack_sc_device_interrupt(vector);
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} else {
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handle_irq(16+i);
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}
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}
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}
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static void __init
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rx164_init_irq(void)
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{
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long i;
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rx164_update_irq_hw(0);
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for (i = 16; i < 40; ++i) {
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irq_desc[i].status = IRQ_DISABLED | IRQ_LEVEL;
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irq_desc[i].chip = &rx164_irq_type;
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}
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init_i8259a_irqs();
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common_init_isa_dma();
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setup_irq(16+20, &isa_cascade_irqaction);
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}
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/*
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* The RX164 changed its interrupt routing between pass1 and pass2...
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*
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* PASS1:
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*
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* Slot IDSEL INTA INTB INTC INTD
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* 0 6 5 10 15 20
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* 1 7 4 9 14 19
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* 2 5 3 8 13 18
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* 3 9 2 7 12 17
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* 4 10 1 6 11 16
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*
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* PASS2:
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* Slot IDSEL INTA INTB INTC INTD
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* 0 5 1 7 12 17
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* 1 6 2 8 13 18
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* 2 8 3 9 14 19
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* 3 9 4 10 15 20
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* 4 10 5 11 16 6
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*
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*/
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/*
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* IdSel
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* 5 32 bit PCI option slot 0
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* 6 64 bit PCI option slot 1
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* 7 PCI-ISA bridge
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* 7 64 bit PCI option slot 2
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* 9 32 bit PCI option slot 3
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* 10 PCI-PCI bridge
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*
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*/
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static int __init
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rx164_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
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{
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#if 0
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static char irq_tab_pass1[6][5] __initdata = {
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/*INT INTA INTB INTC INTD */
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{ 16+3, 16+3, 16+8, 16+13, 16+18}, /* IdSel 5, slot 2 */
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{ 16+5, 16+5, 16+10, 16+15, 16+20}, /* IdSel 6, slot 0 */
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{ 16+4, 16+4, 16+9, 16+14, 16+19}, /* IdSel 7, slot 1 */
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{ -1, -1, -1, -1, -1}, /* IdSel 8, PCI/ISA bridge */
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{ 16+2, 16+2, 16+7, 16+12, 16+17}, /* IdSel 9, slot 3 */
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{ 16+1, 16+1, 16+6, 16+11, 16+16}, /* IdSel 10, slot 4 */
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};
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#else
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static char irq_tab[6][5] __initdata = {
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/*INT INTA INTB INTC INTD */
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{ 16+0, 16+0, 16+6, 16+11, 16+16}, /* IdSel 5, slot 0 */
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{ 16+1, 16+1, 16+7, 16+12, 16+17}, /* IdSel 6, slot 1 */
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{ -1, -1, -1, -1, -1}, /* IdSel 7, PCI/ISA bridge */
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{ 16+2, 16+2, 16+8, 16+13, 16+18}, /* IdSel 8, slot 2 */
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{ 16+3, 16+3, 16+9, 16+14, 16+19}, /* IdSel 9, slot 3 */
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{ 16+4, 16+4, 16+10, 16+15, 16+5}, /* IdSel 10, PCI-PCI */
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};
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#endif
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const long min_idsel = 5, max_idsel = 10, irqs_per_slot = 5;
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/* JRP - Need to figure out how to distinguish pass1 from pass2,
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and use the correct table. */
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return COMMON_TABLE_LOOKUP;
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}
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/*
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* The System Vector
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*/
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struct alpha_machine_vector rx164_mv __initmv = {
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.vector_name = "RX164",
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DO_EV5_MMU,
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DO_DEFAULT_RTC,
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DO_POLARIS_IO,
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.machine_check = polaris_machine_check,
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.max_isa_dma_address = ALPHA_MAX_ISA_DMA_ADDRESS,
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.min_io_address = DEFAULT_IO_BASE,
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.min_mem_address = DEFAULT_MEM_BASE,
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.nr_irqs = 40,
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.device_interrupt = rx164_device_interrupt,
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.init_arch = polaris_init_arch,
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.init_irq = rx164_init_irq,
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.init_rtc = common_init_rtc,
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.init_pci = common_init_pci,
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.kill_arch = NULL,
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.pci_map_irq = rx164_map_irq,
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.pci_swizzle = common_swizzle,
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};
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ALIAS_MV(rx164)
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