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44377f622e
The defines and typedefs (hw_interrupt_type, no_irq_type, irq_desc_t) have been kept around for migration reasons. After more than two years it's time to remove them finally. This patch cleans up one of the remaining users. When all such patches hit mainline we can remove the defines and typedefs finally. Impact: cleanup Convert the last remaining users to struct irq_chip and remove the define. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Cc: Richard Henderson <rth@twiddle.net> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
361 lines
8.9 KiB
C
361 lines
8.9 KiB
C
/*
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* linux/arch/alpha/kernel/sys_wildfire.c
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*
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* Wildfire support.
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*
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* Copyright (C) 2000 Andrea Arcangeli <andrea@suse.de> SuSE
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*/
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#include <linux/kernel.h>
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#include <linux/types.h>
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#include <linux/mm.h>
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#include <linux/sched.h>
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#include <linux/pci.h>
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#include <linux/init.h>
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#include <linux/bitops.h>
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#include <asm/ptrace.h>
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#include <asm/system.h>
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#include <asm/dma.h>
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#include <asm/irq.h>
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#include <asm/mmu_context.h>
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#include <asm/io.h>
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#include <asm/pgtable.h>
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#include <asm/core_wildfire.h>
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#include <asm/hwrpb.h>
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#include <asm/tlbflush.h>
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#include "proto.h"
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#include "irq_impl.h"
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#include "pci_impl.h"
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#include "machvec_impl.h"
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static unsigned long cached_irq_mask[WILDFIRE_NR_IRQS/(sizeof(long)*8)];
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DEFINE_SPINLOCK(wildfire_irq_lock);
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static int doing_init_irq_hw = 0;
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static void
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wildfire_update_irq_hw(unsigned int irq)
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{
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int qbbno = (irq >> 8) & (WILDFIRE_MAX_QBB - 1);
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int pcano = (irq >> 6) & (WILDFIRE_PCA_PER_QBB - 1);
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wildfire_pca *pca;
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volatile unsigned long * enable0;
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if (!WILDFIRE_PCA_EXISTS(qbbno, pcano)) {
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if (!doing_init_irq_hw) {
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printk(KERN_ERR "wildfire_update_irq_hw:"
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" got irq %d for non-existent PCA %d"
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" on QBB %d.\n",
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irq, pcano, qbbno);
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}
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return;
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}
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pca = WILDFIRE_pca(qbbno, pcano);
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enable0 = (unsigned long *) &pca->pca_int[0].enable; /* ??? */
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*enable0 = cached_irq_mask[qbbno * WILDFIRE_PCA_PER_QBB + pcano];
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mb();
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*enable0;
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}
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static void __init
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wildfire_init_irq_hw(void)
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{
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#if 0
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register wildfire_pca * pca = WILDFIRE_pca(0, 0);
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volatile unsigned long * enable0, * enable1, * enable2, *enable3;
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volatile unsigned long * target0, * target1, * target2, *target3;
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enable0 = (unsigned long *) &pca->pca_int[0].enable;
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enable1 = (unsigned long *) &pca->pca_int[1].enable;
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enable2 = (unsigned long *) &pca->pca_int[2].enable;
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enable3 = (unsigned long *) &pca->pca_int[3].enable;
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target0 = (unsigned long *) &pca->pca_int[0].target;
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target1 = (unsigned long *) &pca->pca_int[1].target;
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target2 = (unsigned long *) &pca->pca_int[2].target;
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target3 = (unsigned long *) &pca->pca_int[3].target;
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*enable0 = *enable1 = *enable2 = *enable3 = 0;
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*target0 = (1UL<<8) | WILDFIRE_QBB(0);
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*target1 = *target2 = *target3 = 0;
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mb();
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*enable0; *enable1; *enable2; *enable3;
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*target0; *target1; *target2; *target3;
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#else
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int i;
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doing_init_irq_hw = 1;
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/* Need to update only once for every possible PCA. */
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for (i = 0; i < WILDFIRE_NR_IRQS; i+=WILDFIRE_IRQ_PER_PCA)
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wildfire_update_irq_hw(i);
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doing_init_irq_hw = 0;
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#endif
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}
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static void
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wildfire_enable_irq(unsigned int irq)
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{
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if (irq < 16)
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i8259a_enable_irq(irq);
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spin_lock(&wildfire_irq_lock);
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set_bit(irq, &cached_irq_mask);
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wildfire_update_irq_hw(irq);
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spin_unlock(&wildfire_irq_lock);
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}
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static void
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wildfire_disable_irq(unsigned int irq)
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{
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if (irq < 16)
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i8259a_disable_irq(irq);
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spin_lock(&wildfire_irq_lock);
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clear_bit(irq, &cached_irq_mask);
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wildfire_update_irq_hw(irq);
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spin_unlock(&wildfire_irq_lock);
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}
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static void
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wildfire_mask_and_ack_irq(unsigned int irq)
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{
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if (irq < 16)
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i8259a_mask_and_ack_irq(irq);
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spin_lock(&wildfire_irq_lock);
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clear_bit(irq, &cached_irq_mask);
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wildfire_update_irq_hw(irq);
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spin_unlock(&wildfire_irq_lock);
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}
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static unsigned int
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wildfire_startup_irq(unsigned int irq)
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{
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wildfire_enable_irq(irq);
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return 0; /* never anything pending */
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}
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static void
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wildfire_end_irq(unsigned int irq)
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{
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#if 0
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if (!irq_desc[irq].action)
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printk("got irq %d\n", irq);
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#endif
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if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
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wildfire_enable_irq(irq);
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}
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static struct irq_chip wildfire_irq_type = {
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.typename = "WILDFIRE",
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.startup = wildfire_startup_irq,
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.shutdown = wildfire_disable_irq,
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.enable = wildfire_enable_irq,
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.disable = wildfire_disable_irq,
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.ack = wildfire_mask_and_ack_irq,
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.end = wildfire_end_irq,
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};
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static void __init
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wildfire_init_irq_per_pca(int qbbno, int pcano)
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{
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int i, irq_bias;
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unsigned long io_bias;
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static struct irqaction isa_enable = {
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.handler = no_action,
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.name = "isa_enable",
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};
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irq_bias = qbbno * (WILDFIRE_PCA_PER_QBB * WILDFIRE_IRQ_PER_PCA)
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+ pcano * WILDFIRE_IRQ_PER_PCA;
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/* Only need the following for first PCI bus per PCA. */
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io_bias = WILDFIRE_IO(qbbno, pcano<<1) - WILDFIRE_IO_BIAS;
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#if 0
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outb(0, DMA1_RESET_REG + io_bias);
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outb(0, DMA2_RESET_REG + io_bias);
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outb(DMA_MODE_CASCADE, DMA2_MODE_REG + io_bias);
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outb(0, DMA2_MASK_REG + io_bias);
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#endif
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#if 0
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/* ??? Not sure how to do this, yet... */
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init_i8259a_irqs(); /* ??? */
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#endif
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for (i = 0; i < 16; ++i) {
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if (i == 2)
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continue;
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irq_desc[i+irq_bias].status = IRQ_DISABLED | IRQ_LEVEL;
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irq_desc[i+irq_bias].chip = &wildfire_irq_type;
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}
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irq_desc[36+irq_bias].status = IRQ_DISABLED | IRQ_LEVEL;
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irq_desc[36+irq_bias].chip = &wildfire_irq_type;
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for (i = 40; i < 64; ++i) {
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irq_desc[i+irq_bias].status = IRQ_DISABLED | IRQ_LEVEL;
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irq_desc[i+irq_bias].chip = &wildfire_irq_type;
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}
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setup_irq(32+irq_bias, &isa_enable);
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}
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static void __init
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wildfire_init_irq(void)
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{
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int qbbno, pcano;
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#if 1
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wildfire_init_irq_hw();
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init_i8259a_irqs();
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#endif
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for (qbbno = 0; qbbno < WILDFIRE_MAX_QBB; qbbno++) {
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if (WILDFIRE_QBB_EXISTS(qbbno)) {
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for (pcano = 0; pcano < WILDFIRE_PCA_PER_QBB; pcano++) {
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if (WILDFIRE_PCA_EXISTS(qbbno, pcano)) {
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wildfire_init_irq_per_pca(qbbno, pcano);
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}
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}
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}
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}
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}
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static void
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wildfire_device_interrupt(unsigned long vector)
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{
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int irq;
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irq = (vector - 0x800) >> 4;
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/*
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* bits 10-8: source QBB ID
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* bits 7-6: PCA
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* bits 5-0: irq in PCA
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*/
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handle_irq(irq);
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return;
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}
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/*
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* PCI Fixup configuration.
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*
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* Summary per PCA (2 PCI or HIPPI buses):
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*
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* Bit Meaning
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* 0-15 ISA
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*
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*32 ISA summary
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*33 SMI
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*34 NMI
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*36 builtin QLogic SCSI (or slot 0 if no IO module)
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*40 Interrupt Line A from slot 2 PCI0
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*41 Interrupt Line B from slot 2 PCI0
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*42 Interrupt Line C from slot 2 PCI0
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*43 Interrupt Line D from slot 2 PCI0
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*44 Interrupt Line A from slot 3 PCI0
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*45 Interrupt Line B from slot 3 PCI0
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*46 Interrupt Line C from slot 3 PCI0
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*47 Interrupt Line D from slot 3 PCI0
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*
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*48 Interrupt Line A from slot 4 PCI1
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*49 Interrupt Line B from slot 4 PCI1
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*50 Interrupt Line C from slot 4 PCI1
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*51 Interrupt Line D from slot 4 PCI1
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*52 Interrupt Line A from slot 5 PCI1
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*53 Interrupt Line B from slot 5 PCI1
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*54 Interrupt Line C from slot 5 PCI1
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*55 Interrupt Line D from slot 5 PCI1
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*56 Interrupt Line A from slot 6 PCI1
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*57 Interrupt Line B from slot 6 PCI1
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*58 Interrupt Line C from slot 6 PCI1
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*50 Interrupt Line D from slot 6 PCI1
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*60 Interrupt Line A from slot 7 PCI1
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*61 Interrupt Line B from slot 7 PCI1
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*62 Interrupt Line C from slot 7 PCI1
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*63 Interrupt Line D from slot 7 PCI1
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*
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*
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* IdSel
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* 0 Cypress Bridge I/O (ISA summary interrupt)
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* 1 64 bit PCI 0 option slot 1 (SCSI QLogic builtin)
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* 2 64 bit PCI 0 option slot 2
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* 3 64 bit PCI 0 option slot 3
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* 4 64 bit PCI 1 option slot 4
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* 5 64 bit PCI 1 option slot 5
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* 6 64 bit PCI 1 option slot 6
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* 7 64 bit PCI 1 option slot 7
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*/
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static int __init
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wildfire_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
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{
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static char irq_tab[8][5] __initdata = {
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/*INT INTA INTB INTC INTD */
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{ -1, -1, -1, -1, -1}, /* IdSel 0 ISA Bridge */
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{ 36, 36, 36+1, 36+2, 36+3}, /* IdSel 1 SCSI builtin */
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{ 40, 40, 40+1, 40+2, 40+3}, /* IdSel 2 PCI 0 slot 2 */
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{ 44, 44, 44+1, 44+2, 44+3}, /* IdSel 3 PCI 0 slot 3 */
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{ 48, 48, 48+1, 48+2, 48+3}, /* IdSel 4 PCI 1 slot 4 */
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{ 52, 52, 52+1, 52+2, 52+3}, /* IdSel 5 PCI 1 slot 5 */
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{ 56, 56, 56+1, 56+2, 56+3}, /* IdSel 6 PCI 1 slot 6 */
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{ 60, 60, 60+1, 60+2, 60+3}, /* IdSel 7 PCI 1 slot 7 */
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};
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long min_idsel = 0, max_idsel = 7, irqs_per_slot = 5;
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struct pci_controller *hose = dev->sysdata;
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int irq = COMMON_TABLE_LOOKUP;
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if (irq > 0) {
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int qbbno = hose->index >> 3;
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int pcano = (hose->index >> 1) & 3;
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irq += (qbbno << 8) + (pcano << 6);
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}
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return irq;
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}
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/*
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* The System Vectors
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*/
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struct alpha_machine_vector wildfire_mv __initmv = {
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.vector_name = "WILDFIRE",
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DO_EV6_MMU,
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DO_DEFAULT_RTC,
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DO_WILDFIRE_IO,
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.machine_check = wildfire_machine_check,
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.max_isa_dma_address = ALPHA_MAX_ISA_DMA_ADDRESS,
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.min_io_address = DEFAULT_IO_BASE,
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.min_mem_address = DEFAULT_MEM_BASE,
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.nr_irqs = WILDFIRE_NR_IRQS,
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.device_interrupt = wildfire_device_interrupt,
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.init_arch = wildfire_init_arch,
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.init_irq = wildfire_init_irq,
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.init_rtc = common_init_rtc,
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.init_pci = common_init_pci,
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.kill_arch = wildfire_kill_arch,
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.pci_map_irq = wildfire_map_irq,
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.pci_swizzle = common_swizzle,
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.pa_to_nid = wildfire_pa_to_nid,
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.cpuid_to_nid = wildfire_cpuid_to_nid,
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.node_mem_start = wildfire_node_mem_start,
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.node_mem_size = wildfire_node_mem_size,
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};
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ALIAS_MV(wildfire)
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