Christoffer Dall 6cca9100db KVM: arm64: Only sign-extend MMIO up to register width ... commit b6ae256afd upstream. On AArch64 you can do a sign-extended load to either a 32-bit or 64-bit register, and we should only sign extend the register up to the width of the register as specified in the operation (by using the 32-bit Wn or 64-bit Xn register specifier). As it turns out, the architecture provides this decoding information in the SF ("Sixty-Four" -- how cute...) bit. Let's take advantage of this with the usual 32-bit/64-bit header file dance and do the right thing on AArch64 hosts. Signed-off-by: Christoffer Dall <christoffer.dall@arm.com> Signed-off-by: Marc Zyngier <maz@kernel.org> Cc: stable@vger.kernel.org Link: https://lore.kernel.org/r/20191212195055.5541-1-christoffer.dall@arm.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>		2020-02-11 04:35:16 -08:00
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asm	KVM: arm64: Only sign-extend MMIO up to register width	2020-02-11 04:35:16 -08:00
debug	Renesas ARM SoC updates for v5.4	2019-09-03 23:12:58 +02:00
uapi/asm	KVM: arm/arm64: vgic: Allow more than 256 vcpus for KVM_IRQ_LINE	2019-09-09 12:29:09 +01:00