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![James Hogan](/assets/img/avatar_default.png)
Add memory management files for metag. Meta's 32bit virtual address space is split into two halves: - local (0x08000000-0x7fffffff): traditionally local to a hardware thread and incoherent between hardware threads. Each hardware thread has it's own local MMU table. On Meta2 the local space can be globally coherent (GCOn) if the cache partitions coincide. - global (0x88000000-0xffff0000): coherent and traditionally global between hardware threads. On Meta2, each hardware thread has it's own global MMU table. The low 128MiB of each half is non-MMUable and maps directly to the physical address space: - 0x00010000-0x07ffffff: contains Meta core registers and maps SoC bus - 0x80000000-0x87ffffff: contains low latency global core memories Linux usually further splits the local virtual address space like this: - 0x08000000-0x3fffffff: user mappings - 0x40000000-0x7fffffff: kernel mappings Signed-off-by: James Hogan <james.hogan@imgtec.com>
207 lines
5.1 KiB
C
207 lines
5.1 KiB
C
/*
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* Copyright (C) 2008,2009,2010,2011 Imagination Technologies Ltd.
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*
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* Meta 2 enhanced mode MMU handling code.
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*
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*/
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#include <linux/mm.h>
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/io.h>
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#include <linux/bootmem.h>
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#include <linux/syscore_ops.h>
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#include <asm/mmu.h>
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#include <asm/mmu_context.h>
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unsigned long mmu_read_first_level_page(unsigned long vaddr)
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{
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unsigned int cpu = hard_processor_id();
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unsigned long offset, linear_base, linear_limit;
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unsigned int phys0;
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pgd_t *pgd, entry;
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if (is_global_space(vaddr))
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vaddr &= ~0x80000000;
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offset = vaddr >> PGDIR_SHIFT;
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phys0 = metag_in32(mmu_phys0_addr(cpu));
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/* Top bit of linear base is always zero. */
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linear_base = (phys0 >> PGDIR_SHIFT) & 0x1ff;
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/* Limit in the range 0 (4MB) to 9 (2GB). */
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linear_limit = 1 << ((phys0 >> 8) & 0xf);
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linear_limit += linear_base;
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/*
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* If offset is below linear base or above the limit then no
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* mapping exists.
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*/
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if (offset < linear_base || offset > linear_limit)
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return 0;
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offset -= linear_base;
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pgd = (pgd_t *)mmu_get_base();
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entry = pgd[offset];
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return pgd_val(entry);
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}
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unsigned long mmu_read_second_level_page(unsigned long vaddr)
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{
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return __builtin_meta2_cacherd((void *)(vaddr & PAGE_MASK));
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}
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unsigned long mmu_get_base(void)
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{
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unsigned int cpu = hard_processor_id();
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unsigned long stride;
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stride = cpu * LINSYSMEMTnX_STRIDE;
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/*
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* Bits 18:2 of the MMCU_TnLocal_TABLE_PHYS1 register should be
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* used as an offset to the start of the top-level pgd table.
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*/
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stride += (metag_in32(mmu_phys1_addr(cpu)) & 0x7fffc);
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if (is_global_space(PAGE_OFFSET))
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stride += LINSYSMEMTXG_OFFSET;
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return LINSYSMEMT0L_BASE + stride;
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}
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#define FIRST_LEVEL_MASK 0xffffffc0
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#define SECOND_LEVEL_MASK 0xfffff000
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#define SECOND_LEVEL_ALIGN 64
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static void repriv_mmu_tables(void)
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{
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unsigned long phys0_addr;
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unsigned int g;
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/*
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* Check that all the mmu table regions are priv protected, and if not
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* fix them and emit a warning. If we left them without priv protection
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* then userland processes would have access to a 2M window into
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* physical memory near where the page tables are.
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*/
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phys0_addr = MMCU_T0LOCAL_TABLE_PHYS0;
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for (g = 0; g < 2; ++g) {
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unsigned int t, phys0;
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unsigned long flags;
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for (t = 0; t < 4; ++t) {
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__global_lock2(flags);
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phys0 = metag_in32(phys0_addr);
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if ((phys0 & _PAGE_PRESENT) && !(phys0 & _PAGE_PRIV)) {
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pr_warn("Fixing priv protection on T%d %s MMU table region\n",
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t,
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g ? "global" : "local");
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phys0 |= _PAGE_PRIV;
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metag_out32(phys0, phys0_addr);
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}
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__global_unlock2(flags);
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phys0_addr += MMCU_TnX_TABLE_PHYSX_STRIDE;
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}
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phys0_addr += MMCU_TXG_TABLE_PHYSX_OFFSET
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- 4*MMCU_TnX_TABLE_PHYSX_STRIDE;
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}
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}
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#ifdef CONFIG_METAG_SUSPEND_MEM
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static void mmu_resume(void)
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{
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/*
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* If a full suspend to RAM has happened then the original bad MMU table
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* priv may have been restored, so repriv them again.
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*/
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repriv_mmu_tables();
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}
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#else
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#define mmu_resume NULL
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#endif /* CONFIG_METAG_SUSPEND_MEM */
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static struct syscore_ops mmu_syscore_ops = {
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.resume = mmu_resume,
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};
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void __init mmu_init(unsigned long mem_end)
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{
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unsigned long entry, addr;
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pgd_t *p_swapper_pg_dir;
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#ifdef CONFIG_KERNEL_4M_PAGES
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unsigned long mem_size = mem_end - PAGE_OFFSET;
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unsigned int pages = DIV_ROUND_UP(mem_size, 1 << 22);
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unsigned int second_level_entry = 0;
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unsigned long *second_level_table;
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#endif
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/*
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* Now copy over any MMU pgd entries already in the mmu page tables
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* over to our root init process (swapper_pg_dir) map. This map is
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* then inherited by all other processes, which means all processes
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* inherit a map of the kernel space.
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*/
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addr = META_MEMORY_BASE;
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entry = pgd_index(META_MEMORY_BASE);
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p_swapper_pg_dir = pgd_offset_k(0) + entry;
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while (entry < (PTRS_PER_PGD - pgd_index(META_MEMORY_BASE))) {
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unsigned long pgd_entry;
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/* copy over the current MMU value */
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pgd_entry = mmu_read_first_level_page(addr);
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pgd_val(*p_swapper_pg_dir) = pgd_entry;
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p_swapper_pg_dir++;
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addr += PGDIR_SIZE;
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entry++;
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}
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#ifdef CONFIG_KERNEL_4M_PAGES
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/*
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* At this point we can also map the kernel with 4MB pages to
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* reduce TLB pressure.
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*/
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second_level_table = alloc_bootmem_pages(SECOND_LEVEL_ALIGN * pages);
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addr = PAGE_OFFSET;
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entry = pgd_index(PAGE_OFFSET);
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p_swapper_pg_dir = pgd_offset_k(0) + entry;
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while (pages > 0) {
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unsigned long phys_addr, second_level_phys;
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pte_t *pte = (pte_t *)&second_level_table[second_level_entry];
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phys_addr = __pa(addr);
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second_level_phys = __pa(pte);
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pgd_val(*p_swapper_pg_dir) = ((second_level_phys &
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FIRST_LEVEL_MASK) |
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_PAGE_SZ_4M |
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_PAGE_PRESENT);
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pte_val(*pte) = ((phys_addr & SECOND_LEVEL_MASK) |
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_PAGE_PRESENT | _PAGE_DIRTY |
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_PAGE_ACCESSED | _PAGE_WRITE |
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_PAGE_CACHEABLE | _PAGE_KERNEL);
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p_swapper_pg_dir++;
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addr += PGDIR_SIZE;
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/* Second level pages must be 64byte aligned. */
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second_level_entry += (SECOND_LEVEL_ALIGN /
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sizeof(unsigned long));
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pages--;
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}
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load_pgd(swapper_pg_dir, hard_processor_id());
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flush_tlb_all();
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#endif
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repriv_mmu_tables();
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register_syscore_ops(&mmu_syscore_ops);
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}
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