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![Aneesh Kumar K.V](/assets/img/avatar_default.png)
upatepp can get called for a nohpte fault when we find from the linux page table that the translation was hashed before. In that case we are sure that there is no existing translation, hence we could avoid doing tlbie. We could possibly race with a parallel fault filling the TLB. But that should be ok because updatepp is only ever relaxing permissions. We also look at linux pte permission bits when filling hash pte permission bits. We also hold the linux pte busy bits while inserting/updating a hashpte entry, hence a paralle update of linux pte is not possible. On the other hand mprotect involves ptep_modify_prot_start which cause a hpte invalidate and not updatepp. Performance number: We use randbox_access_bench written by Anton. Kernel with THP disabled and smaller hash page table size. 86.60% random_access_b [kernel.kallsyms] [k] .native_hpte_updatepp 2.10% random_access_b random_access_bench [.] doit 1.99% random_access_b [kernel.kallsyms] [k] .do_raw_spin_lock 1.85% random_access_b [kernel.kallsyms] [k] .native_hpte_insert 1.26% random_access_b [kernel.kallsyms] [k] .native_flush_hash_range 1.18% random_access_b [kernel.kallsyms] [k] .__delay 0.69% random_access_b [kernel.kallsyms] [k] .native_hpte_remove 0.37% random_access_b [kernel.kallsyms] [k] .clear_user_page 0.34% random_access_b [kernel.kallsyms] [k] .__hash_page_64K 0.32% random_access_b [kernel.kallsyms] [k] fast_exception_return 0.30% random_access_b [kernel.kallsyms] [k] .hash_page_mm With Fix: 27.54% random_access_b random_access_bench [.] doit 22.90% random_access_b [kernel.kallsyms] [k] .native_hpte_insert 5.76% random_access_b [kernel.kallsyms] [k] .native_hpte_remove 5.20% random_access_b [kernel.kallsyms] [k] fast_exception_return 5.12% random_access_b [kernel.kallsyms] [k] .__hash_page_64K 4.80% random_access_b [kernel.kallsyms] [k] .hash_page_mm 3.31% random_access_b [kernel.kallsyms] [k] data_access_common 1.84% random_access_b [kernel.kallsyms] [k] .trace_hardirqs_on_caller Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
129 lines
3.8 KiB
C
129 lines
3.8 KiB
C
/*
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* PPC64 Huge TLB Page Support for hash based MMUs (POWER4 and later)
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*
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* Copyright (C) 2003 David Gibson, IBM Corporation.
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*
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* Based on the IA-32 version:
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* Copyright (C) 2002, Rohit Seth <rohit.seth@intel.com>
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*/
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#include <linux/mm.h>
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#include <linux/hugetlb.h>
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#include <asm/pgtable.h>
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#include <asm/pgalloc.h>
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#include <asm/cacheflush.h>
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#include <asm/machdep.h>
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extern long hpte_insert_repeating(unsigned long hash, unsigned long vpn,
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unsigned long pa, unsigned long rlags,
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unsigned long vflags, int psize, int ssize);
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int __hash_page_huge(unsigned long ea, unsigned long access, unsigned long vsid,
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pte_t *ptep, unsigned long trap, unsigned long flags,
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int ssize, unsigned int shift, unsigned int mmu_psize)
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{
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unsigned long vpn;
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unsigned long old_pte, new_pte;
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unsigned long rflags, pa, sz;
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long slot;
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BUG_ON(shift != mmu_psize_defs[mmu_psize].shift);
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/* Search the Linux page table for a match with va */
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vpn = hpt_vpn(ea, vsid, ssize);
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/* At this point, we have a pte (old_pte) which can be used to build
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* or update an HPTE. There are 2 cases:
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*
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* 1. There is a valid (present) pte with no associated HPTE (this is
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* the most common case)
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* 2. There is a valid (present) pte with an associated HPTE. The
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* current values of the pp bits in the HPTE prevent access
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* because we are doing software DIRTY bit management and the
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* page is currently not DIRTY.
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*/
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do {
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old_pte = pte_val(*ptep);
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/* If PTE busy, retry the access */
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if (unlikely(old_pte & _PAGE_BUSY))
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return 0;
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/* If PTE permissions don't match, take page fault */
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if (unlikely(access & ~old_pte))
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return 1;
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/* Try to lock the PTE, add ACCESSED and DIRTY if it was
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* a write access */
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new_pte = old_pte | _PAGE_BUSY | _PAGE_ACCESSED;
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if (access & _PAGE_RW)
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new_pte |= _PAGE_DIRTY;
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} while(old_pte != __cmpxchg_u64((unsigned long *)ptep,
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old_pte, new_pte));
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rflags = 0x2 | (!(new_pte & _PAGE_RW));
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/* _PAGE_EXEC -> HW_NO_EXEC since it's inverted */
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rflags |= ((new_pte & _PAGE_EXEC) ? 0 : HPTE_R_N);
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sz = ((1UL) << shift);
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if (!cpu_has_feature(CPU_FTR_COHERENT_ICACHE))
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/* No CPU has hugepages but lacks no execute, so we
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* don't need to worry about that case */
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rflags = hash_page_do_lazy_icache(rflags, __pte(old_pte), trap);
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/* Check if pte already has an hpte (case 2) */
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if (unlikely(old_pte & _PAGE_HASHPTE)) {
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/* There MIGHT be an HPTE for this pte */
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unsigned long hash, slot;
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hash = hpt_hash(vpn, shift, ssize);
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if (old_pte & _PAGE_F_SECOND)
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hash = ~hash;
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slot = (hash & htab_hash_mask) * HPTES_PER_GROUP;
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slot += (old_pte & _PAGE_F_GIX) >> 12;
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if (ppc_md.hpte_updatepp(slot, rflags, vpn, mmu_psize,
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mmu_psize, ssize, flags) == -1)
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old_pte &= ~_PAGE_HPTEFLAGS;
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}
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if (likely(!(old_pte & _PAGE_HASHPTE))) {
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unsigned long hash = hpt_hash(vpn, shift, ssize);
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pa = pte_pfn(__pte(old_pte)) << PAGE_SHIFT;
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/* clear HPTE slot informations in new PTE */
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#ifdef CONFIG_PPC_64K_PAGES
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new_pte = (new_pte & ~_PAGE_HPTEFLAGS) | _PAGE_HPTE_SUB0;
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#else
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new_pte = (new_pte & ~_PAGE_HPTEFLAGS) | _PAGE_HASHPTE;
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#endif
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/* Add in WIMG bits */
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rflags |= (new_pte & (_PAGE_WRITETHRU | _PAGE_NO_CACHE |
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_PAGE_COHERENT | _PAGE_GUARDED));
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/*
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* enable the memory coherence always
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*/
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rflags |= HPTE_R_M;
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slot = hpte_insert_repeating(hash, vpn, pa, rflags, 0,
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mmu_psize, ssize);
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/*
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* Hypervisor failure. Restore old pte and return -1
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* similar to __hash_page_*
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*/
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if (unlikely(slot == -2)) {
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*ptep = __pte(old_pte);
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hash_failure_debug(ea, access, vsid, trap, ssize,
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mmu_psize, mmu_psize, old_pte);
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return -1;
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}
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new_pte |= (slot << 12) & (_PAGE_F_SECOND | _PAGE_F_GIX);
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}
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/*
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* No need to use ldarx/stdcx here
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*/
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*ptep = __pte(new_pte & ~_PAGE_BUSY);
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return 0;
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}
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