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![Linus Torvalds](/assets/img/avatar_default.png)
Here's the set of driver core patches for 3.19-rc1. They are dominated by the removal of the .owner field in platform drivers. They touch a lot of files, but they are "simple" changes, just removing a line in a structure. Other than that, a few minor driver core and debugfs changes. There are some ath9k patches coming in through this tree that have been acked by the wireless maintainers as they relied on the debugfs changes. Everything has been in linux-next for a while. Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> -----BEGIN PGP SIGNATURE----- Version: GnuPG v2 iEYEABECAAYFAlSOD20ACgkQMUfUDdst+ylLPACg2QrW1oHhdTMT9WI8jihlHVRM 53kAoLeteByQ3iVwWurwwseRPiWa8+MI =OVRS -----END PGP SIGNATURE----- Merge tag 'driver-core-3.19-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/driver-core Pull driver core update from Greg KH: "Here's the set of driver core patches for 3.19-rc1. They are dominated by the removal of the .owner field in platform drivers. They touch a lot of files, but they are "simple" changes, just removing a line in a structure. Other than that, a few minor driver core and debugfs changes. There are some ath9k patches coming in through this tree that have been acked by the wireless maintainers as they relied on the debugfs changes. Everything has been in linux-next for a while" * tag 'driver-core-3.19-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/driver-core: (324 commits) Revert "ath: ath9k: use debugfs_create_devm_seqfile() helper for seq_file entries" fs: debugfs: add forward declaration for struct device type firmware class: Deletion of an unnecessary check before the function call "vunmap" firmware loader: fix hung task warning dump devcoredump: provide a one-way disable function device: Add dev_<level>_once variants ath: ath9k: use debugfs_create_devm_seqfile() helper for seq_file entries ath: use seq_file api for ath9k debugfs files debugfs: add helper function to create device related seq_file drivers/base: cacheinfo: remove noisy error boot message Revert "core: platform: add warning if driver has no owner" drivers: base: support cpu cache information interface to userspace via sysfs drivers: base: add cpu_device_create to support per-cpu devices topology: replace custom attribute macros with standard DEVICE_ATTR* cpumask: factor out show_cpumap into separate helper function driver core: Fix unbalanced device reference in drivers_probe driver core: fix race with userland in device_add() sysfs/kernfs: make read requests on pre-alloc files use the buffer. sysfs/kernfs: allow attributes to request write buffer be pre-allocated. fs: sysfs: return EGBIG on write if offset is larger than file size ...
790 lines
21 KiB
C
790 lines
21 KiB
C
/*
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* Freescale MPC85xx/MPC86xx RapidIO support
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*
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* Copyright 2009 Sysgo AG
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* Thomas Moll <thomas.moll@sysgo.com>
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* - fixed maintenance access routines, check for aligned access
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*
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* Copyright 2009 Integrated Device Technology, Inc.
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* Alex Bounine <alexandre.bounine@idt.com>
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* - Added Port-Write message handling
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* - Added Machine Check exception handling
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*
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* Copyright (C) 2007, 2008, 2010, 2011 Freescale Semiconductor, Inc.
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* Zhang Wei <wei.zhang@freescale.com>
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*
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* Copyright 2005 MontaVista Software, Inc.
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* Matt Porter <mporter@kernel.crashing.org>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/types.h>
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#include <linux/dma-mapping.h>
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#include <linux/interrupt.h>
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#include <linux/device.h>
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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#include <linux/of_platform.h>
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#include <linux/delay.h>
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#include <linux/slab.h>
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#include <linux/io.h>
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#include <linux/uaccess.h>
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#include <asm/machdep.h>
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#include "fsl_rio.h"
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#undef DEBUG_PW /* Port-Write debugging */
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#define RIO_PORT1_EDCSR 0x0640
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#define RIO_PORT2_EDCSR 0x0680
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#define RIO_PORT1_IECSR 0x10130
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#define RIO_PORT2_IECSR 0x101B0
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#define RIO_GCCSR 0x13c
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#define RIO_ESCSR 0x158
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#define ESCSR_CLEAR 0x07120204
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#define RIO_PORT2_ESCSR 0x178
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#define RIO_CCSR 0x15c
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#define RIO_LTLEDCSR_IER 0x80000000
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#define RIO_LTLEDCSR_PRT 0x01000000
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#define IECSR_CLEAR 0x80000000
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#define RIO_ISR_AACR 0x10120
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#define RIO_ISR_AACR_AA 0x1 /* Accept All ID */
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#define RIWTAR_TRAD_VAL_SHIFT 12
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#define RIWTAR_TRAD_MASK 0x00FFFFFF
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#define RIWBAR_BADD_VAL_SHIFT 12
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#define RIWBAR_BADD_MASK 0x003FFFFF
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#define RIWAR_ENABLE 0x80000000
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#define RIWAR_TGINT_LOCAL 0x00F00000
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#define RIWAR_RDTYP_NO_SNOOP 0x00040000
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#define RIWAR_RDTYP_SNOOP 0x00050000
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#define RIWAR_WRTYP_NO_SNOOP 0x00004000
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#define RIWAR_WRTYP_SNOOP 0x00005000
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#define RIWAR_WRTYP_ALLOC 0x00006000
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#define RIWAR_SIZE_MASK 0x0000003F
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#define __fsl_read_rio_config(x, addr, err, op) \
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__asm__ __volatile__( \
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"1: "op" %1,0(%2)\n" \
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" eieio\n" \
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"2:\n" \
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".section .fixup,\"ax\"\n" \
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"3: li %1,-1\n" \
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" li %0,%3\n" \
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" b 2b\n" \
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".section __ex_table,\"a\"\n" \
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PPC_LONG_ALIGN "\n" \
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PPC_LONG "1b,3b\n" \
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".text" \
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: "=r" (err), "=r" (x) \
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: "b" (addr), "i" (-EFAULT), "0" (err))
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void __iomem *rio_regs_win;
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void __iomem *rmu_regs_win;
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resource_size_t rio_law_start;
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struct fsl_rio_dbell *dbell;
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struct fsl_rio_pw *pw;
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#ifdef CONFIG_E500
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int fsl_rio_mcheck_exception(struct pt_regs *regs)
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{
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const struct exception_table_entry *entry;
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unsigned long reason;
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if (!rio_regs_win)
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return 0;
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reason = in_be32((u32 *)(rio_regs_win + RIO_LTLEDCSR));
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if (reason & (RIO_LTLEDCSR_IER | RIO_LTLEDCSR_PRT)) {
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/* Check if we are prepared to handle this fault */
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entry = search_exception_tables(regs->nip);
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if (entry) {
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pr_debug("RIO: %s - MC Exception handled\n",
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__func__);
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out_be32((u32 *)(rio_regs_win + RIO_LTLEDCSR),
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0);
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regs->msr |= MSR_RI;
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regs->nip = entry->fixup;
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return 1;
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}
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}
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return 0;
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}
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EXPORT_SYMBOL_GPL(fsl_rio_mcheck_exception);
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#endif
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/**
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* fsl_local_config_read - Generate a MPC85xx local config space read
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* @mport: RapidIO master port info
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* @index: ID of RapdiIO interface
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* @offset: Offset into configuration space
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* @len: Length (in bytes) of the maintenance transaction
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* @data: Value to be read into
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*
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* Generates a MPC85xx local configuration space read. Returns %0 on
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* success or %-EINVAL on failure.
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*/
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static int fsl_local_config_read(struct rio_mport *mport,
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int index, u32 offset, int len, u32 *data)
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{
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struct rio_priv *priv = mport->priv;
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pr_debug("fsl_local_config_read: index %d offset %8.8x\n", index,
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offset);
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*data = in_be32(priv->regs_win + offset);
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return 0;
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}
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/**
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* fsl_local_config_write - Generate a MPC85xx local config space write
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* @mport: RapidIO master port info
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* @index: ID of RapdiIO interface
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* @offset: Offset into configuration space
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* @len: Length (in bytes) of the maintenance transaction
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* @data: Value to be written
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*
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* Generates a MPC85xx local configuration space write. Returns %0 on
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* success or %-EINVAL on failure.
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*/
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static int fsl_local_config_write(struct rio_mport *mport,
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int index, u32 offset, int len, u32 data)
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{
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struct rio_priv *priv = mport->priv;
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pr_debug
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("fsl_local_config_write: index %d offset %8.8x data %8.8x\n",
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index, offset, data);
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out_be32(priv->regs_win + offset, data);
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return 0;
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}
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/**
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* fsl_rio_config_read - Generate a MPC85xx read maintenance transaction
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* @mport: RapidIO master port info
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* @index: ID of RapdiIO interface
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* @destid: Destination ID of transaction
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* @hopcount: Number of hops to target device
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* @offset: Offset into configuration space
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* @len: Length (in bytes) of the maintenance transaction
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* @val: Location to be read into
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*
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* Generates a MPC85xx read maintenance transaction. Returns %0 on
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* success or %-EINVAL on failure.
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*/
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static int
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fsl_rio_config_read(struct rio_mport *mport, int index, u16 destid,
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u8 hopcount, u32 offset, int len, u32 *val)
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{
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struct rio_priv *priv = mport->priv;
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u8 *data;
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u32 rval, err = 0;
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pr_debug
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("fsl_rio_config_read:"
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" index %d destid %d hopcount %d offset %8.8x len %d\n",
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index, destid, hopcount, offset, len);
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/* 16MB maintenance window possible */
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/* allow only aligned access to maintenance registers */
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if (offset > (0x1000000 - len) || !IS_ALIGNED(offset, len))
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return -EINVAL;
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out_be32(&priv->maint_atmu_regs->rowtar,
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(destid << 22) | (hopcount << 12) | (offset >> 12));
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out_be32(&priv->maint_atmu_regs->rowtear, (destid >> 10));
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data = (u8 *) priv->maint_win + (offset & (RIO_MAINT_WIN_SIZE - 1));
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switch (len) {
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case 1:
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__fsl_read_rio_config(rval, data, err, "lbz");
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break;
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case 2:
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__fsl_read_rio_config(rval, data, err, "lhz");
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break;
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case 4:
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__fsl_read_rio_config(rval, data, err, "lwz");
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break;
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default:
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return -EINVAL;
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}
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if (err) {
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pr_debug("RIO: cfg_read error %d for %x:%x:%x\n",
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err, destid, hopcount, offset);
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}
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*val = rval;
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return err;
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}
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/**
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* fsl_rio_config_write - Generate a MPC85xx write maintenance transaction
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* @mport: RapidIO master port info
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* @index: ID of RapdiIO interface
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* @destid: Destination ID of transaction
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* @hopcount: Number of hops to target device
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* @offset: Offset into configuration space
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* @len: Length (in bytes) of the maintenance transaction
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* @val: Value to be written
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*
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* Generates an MPC85xx write maintenance transaction. Returns %0 on
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* success or %-EINVAL on failure.
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*/
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static int
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fsl_rio_config_write(struct rio_mport *mport, int index, u16 destid,
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u8 hopcount, u32 offset, int len, u32 val)
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{
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struct rio_priv *priv = mport->priv;
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u8 *data;
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pr_debug
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("fsl_rio_config_write:"
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" index %d destid %d hopcount %d offset %8.8x len %d val %8.8x\n",
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index, destid, hopcount, offset, len, val);
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/* 16MB maintenance windows possible */
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/* allow only aligned access to maintenance registers */
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if (offset > (0x1000000 - len) || !IS_ALIGNED(offset, len))
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return -EINVAL;
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out_be32(&priv->maint_atmu_regs->rowtar,
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(destid << 22) | (hopcount << 12) | (offset >> 12));
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out_be32(&priv->maint_atmu_regs->rowtear, (destid >> 10));
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data = (u8 *) priv->maint_win + (offset & (RIO_MAINT_WIN_SIZE - 1));
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switch (len) {
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case 1:
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out_8((u8 *) data, val);
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break;
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case 2:
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out_be16((u16 *) data, val);
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break;
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case 4:
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out_be32((u32 *) data, val);
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break;
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default:
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return -EINVAL;
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}
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return 0;
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}
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static void fsl_rio_inbound_mem_init(struct rio_priv *priv)
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{
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int i;
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/* close inbound windows */
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for (i = 0; i < RIO_INB_ATMU_COUNT; i++)
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out_be32(&priv->inb_atmu_regs[i].riwar, 0);
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}
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int fsl_map_inb_mem(struct rio_mport *mport, dma_addr_t lstart,
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u64 rstart, u32 size, u32 flags)
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{
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struct rio_priv *priv = mport->priv;
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u32 base_size;
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unsigned int base_size_log;
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u64 win_start, win_end;
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u32 riwar;
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int i;
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if ((size & (size - 1)) != 0)
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return -EINVAL;
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base_size_log = ilog2(size);
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base_size = 1 << base_size_log;
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/* check if addresses are aligned with the window size */
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if (lstart & (base_size - 1))
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return -EINVAL;
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if (rstart & (base_size - 1))
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return -EINVAL;
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/* check for conflicting ranges */
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for (i = 0; i < RIO_INB_ATMU_COUNT; i++) {
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riwar = in_be32(&priv->inb_atmu_regs[i].riwar);
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if ((riwar & RIWAR_ENABLE) == 0)
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continue;
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win_start = ((u64)(in_be32(&priv->inb_atmu_regs[i].riwbar) & RIWBAR_BADD_MASK))
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<< RIWBAR_BADD_VAL_SHIFT;
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win_end = win_start + ((1 << ((riwar & RIWAR_SIZE_MASK) + 1)) - 1);
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if (rstart < win_end && (rstart + size) > win_start)
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return -EINVAL;
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}
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/* find unused atmu */
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for (i = 0; i < RIO_INB_ATMU_COUNT; i++) {
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riwar = in_be32(&priv->inb_atmu_regs[i].riwar);
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if ((riwar & RIWAR_ENABLE) == 0)
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break;
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}
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if (i >= RIO_INB_ATMU_COUNT)
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return -ENOMEM;
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out_be32(&priv->inb_atmu_regs[i].riwtar, lstart >> RIWTAR_TRAD_VAL_SHIFT);
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out_be32(&priv->inb_atmu_regs[i].riwbar, rstart >> RIWBAR_BADD_VAL_SHIFT);
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out_be32(&priv->inb_atmu_regs[i].riwar, RIWAR_ENABLE | RIWAR_TGINT_LOCAL |
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RIWAR_RDTYP_SNOOP | RIWAR_WRTYP_SNOOP | (base_size_log - 1));
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return 0;
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}
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void fsl_unmap_inb_mem(struct rio_mport *mport, dma_addr_t lstart)
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{
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u32 win_start_shift, base_start_shift;
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struct rio_priv *priv = mport->priv;
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u32 riwar, riwtar;
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int i;
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/* skip default window */
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base_start_shift = lstart >> RIWTAR_TRAD_VAL_SHIFT;
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for (i = 0; i < RIO_INB_ATMU_COUNT; i++) {
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riwar = in_be32(&priv->inb_atmu_regs[i].riwar);
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if ((riwar & RIWAR_ENABLE) == 0)
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continue;
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riwtar = in_be32(&priv->inb_atmu_regs[i].riwtar);
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win_start_shift = riwtar & RIWTAR_TRAD_MASK;
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if (win_start_shift == base_start_shift) {
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out_be32(&priv->inb_atmu_regs[i].riwar, riwar & ~RIWAR_ENABLE);
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return;
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}
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}
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}
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void fsl_rio_port_error_handler(int offset)
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{
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/*XXX: Error recovery is not implemented, we just clear errors */
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out_be32((u32 *)(rio_regs_win + RIO_LTLEDCSR), 0);
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if (offset == 0) {
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out_be32((u32 *)(rio_regs_win + RIO_PORT1_EDCSR), 0);
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out_be32((u32 *)(rio_regs_win + RIO_PORT1_IECSR), IECSR_CLEAR);
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out_be32((u32 *)(rio_regs_win + RIO_ESCSR), ESCSR_CLEAR);
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} else {
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out_be32((u32 *)(rio_regs_win + RIO_PORT2_EDCSR), 0);
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out_be32((u32 *)(rio_regs_win + RIO_PORT2_IECSR), IECSR_CLEAR);
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out_be32((u32 *)(rio_regs_win + RIO_PORT2_ESCSR), ESCSR_CLEAR);
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}
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}
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static inline void fsl_rio_info(struct device *dev, u32 ccsr)
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{
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const char *str;
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if (ccsr & 1) {
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/* Serial phy */
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switch (ccsr >> 30) {
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case 0:
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str = "1";
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break;
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case 1:
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str = "4";
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break;
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default:
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str = "Unknown";
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break;
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}
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dev_info(dev, "Hardware port width: %s\n", str);
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switch ((ccsr >> 27) & 7) {
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case 0:
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str = "Single-lane 0";
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break;
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case 1:
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str = "Single-lane 2";
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break;
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case 2:
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str = "Four-lane";
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break;
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default:
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str = "Unknown";
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break;
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}
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dev_info(dev, "Training connection status: %s\n", str);
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} else {
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/* Parallel phy */
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if (!(ccsr & 0x80000000))
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dev_info(dev, "Output port operating in 8-bit mode\n");
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if (!(ccsr & 0x08000000))
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dev_info(dev, "Input port operating in 8-bit mode\n");
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}
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}
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/**
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* fsl_rio_setup - Setup Freescale PowerPC RapidIO interface
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* @dev: platform_device pointer
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*
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* Initializes MPC85xx RapidIO hardware interface, configures
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* master port with system-specific info, and registers the
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* master port with the RapidIO subsystem.
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*/
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int fsl_rio_setup(struct platform_device *dev)
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{
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struct rio_ops *ops;
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struct rio_mport *port;
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struct rio_priv *priv;
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int rc = 0;
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const u32 *dt_range, *cell, *port_index;
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u32 active_ports = 0;
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struct resource regs, rmu_regs;
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struct device_node *np, *rmu_node;
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int rlen;
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u32 ccsr;
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u64 range_start, range_size;
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int paw, aw, sw;
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u32 i;
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static int tmp;
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struct device_node *rmu_np[MAX_MSG_UNIT_NUM] = {NULL};
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if (!dev->dev.of_node) {
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dev_err(&dev->dev, "Device OF-Node is NULL");
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return -ENODEV;
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}
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rc = of_address_to_resource(dev->dev.of_node, 0, ®s);
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if (rc) {
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dev_err(&dev->dev, "Can't get %s property 'reg'\n",
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dev->dev.of_node->full_name);
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return -EFAULT;
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}
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dev_info(&dev->dev, "Of-device full name %s\n",
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dev->dev.of_node->full_name);
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dev_info(&dev->dev, "Regs: %pR\n", ®s);
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rio_regs_win = ioremap(regs.start, resource_size(®s));
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if (!rio_regs_win) {
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dev_err(&dev->dev, "Unable to map rio register window\n");
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rc = -ENOMEM;
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goto err_rio_regs;
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}
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ops = kzalloc(sizeof(struct rio_ops), GFP_KERNEL);
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if (!ops) {
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rc = -ENOMEM;
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goto err_ops;
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}
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ops->lcread = fsl_local_config_read;
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ops->lcwrite = fsl_local_config_write;
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ops->cread = fsl_rio_config_read;
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ops->cwrite = fsl_rio_config_write;
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ops->dsend = fsl_rio_doorbell_send;
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ops->pwenable = fsl_rio_pw_enable;
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ops->open_outb_mbox = fsl_open_outb_mbox;
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ops->open_inb_mbox = fsl_open_inb_mbox;
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ops->close_outb_mbox = fsl_close_outb_mbox;
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ops->close_inb_mbox = fsl_close_inb_mbox;
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ops->add_outb_message = fsl_add_outb_message;
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ops->add_inb_buffer = fsl_add_inb_buffer;
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ops->get_inb_message = fsl_get_inb_message;
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ops->map_inb = fsl_map_inb_mem;
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ops->unmap_inb = fsl_unmap_inb_mem;
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rmu_node = of_parse_phandle(dev->dev.of_node, "fsl,srio-rmu-handle", 0);
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if (!rmu_node) {
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dev_err(&dev->dev, "No valid fsl,srio-rmu-handle property\n");
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goto err_rmu;
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}
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rc = of_address_to_resource(rmu_node, 0, &rmu_regs);
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if (rc) {
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dev_err(&dev->dev, "Can't get %s property 'reg'\n",
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rmu_node->full_name);
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goto err_rmu;
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}
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rmu_regs_win = ioremap(rmu_regs.start, resource_size(&rmu_regs));
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if (!rmu_regs_win) {
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dev_err(&dev->dev, "Unable to map rmu register window\n");
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rc = -ENOMEM;
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goto err_rmu;
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}
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for_each_compatible_node(np, NULL, "fsl,srio-msg-unit") {
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rmu_np[tmp] = np;
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tmp++;
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}
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/*set up doobell node*/
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np = of_find_compatible_node(NULL, NULL, "fsl,srio-dbell-unit");
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if (!np) {
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dev_err(&dev->dev, "No fsl,srio-dbell-unit node\n");
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rc = -ENODEV;
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goto err_dbell;
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}
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dbell = kzalloc(sizeof(struct fsl_rio_dbell), GFP_KERNEL);
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if (!(dbell)) {
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dev_err(&dev->dev, "Can't alloc memory for 'fsl_rio_dbell'\n");
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rc = -ENOMEM;
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goto err_dbell;
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}
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dbell->dev = &dev->dev;
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dbell->bellirq = irq_of_parse_and_map(np, 1);
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dev_info(&dev->dev, "bellirq: %d\n", dbell->bellirq);
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aw = of_n_addr_cells(np);
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dt_range = of_get_property(np, "reg", &rlen);
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if (!dt_range) {
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pr_err("%s: unable to find 'reg' property\n",
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np->full_name);
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rc = -ENOMEM;
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goto err_pw;
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}
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range_start = of_read_number(dt_range, aw);
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dbell->dbell_regs = (struct rio_dbell_regs *)(rmu_regs_win +
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(u32)range_start);
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/*set up port write node*/
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np = of_find_compatible_node(NULL, NULL, "fsl,srio-port-write-unit");
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if (!np) {
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dev_err(&dev->dev, "No fsl,srio-port-write-unit node\n");
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rc = -ENODEV;
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goto err_pw;
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}
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pw = kzalloc(sizeof(struct fsl_rio_pw), GFP_KERNEL);
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if (!(pw)) {
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dev_err(&dev->dev, "Can't alloc memory for 'fsl_rio_pw'\n");
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rc = -ENOMEM;
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goto err_pw;
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}
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pw->dev = &dev->dev;
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pw->pwirq = irq_of_parse_and_map(np, 0);
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dev_info(&dev->dev, "pwirq: %d\n", pw->pwirq);
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aw = of_n_addr_cells(np);
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dt_range = of_get_property(np, "reg", &rlen);
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if (!dt_range) {
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pr_err("%s: unable to find 'reg' property\n",
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np->full_name);
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rc = -ENOMEM;
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goto err;
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}
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range_start = of_read_number(dt_range, aw);
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pw->pw_regs = (struct rio_pw_regs *)(rmu_regs_win + (u32)range_start);
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/*set up ports node*/
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for_each_child_of_node(dev->dev.of_node, np) {
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port_index = of_get_property(np, "cell-index", NULL);
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if (!port_index) {
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dev_err(&dev->dev, "Can't get %s property 'cell-index'\n",
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np->full_name);
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continue;
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}
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dt_range = of_get_property(np, "ranges", &rlen);
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if (!dt_range) {
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dev_err(&dev->dev, "Can't get %s property 'ranges'\n",
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np->full_name);
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continue;
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}
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/* Get node address wide */
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cell = of_get_property(np, "#address-cells", NULL);
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if (cell)
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aw = *cell;
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else
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aw = of_n_addr_cells(np);
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/* Get node size wide */
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cell = of_get_property(np, "#size-cells", NULL);
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if (cell)
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sw = *cell;
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else
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sw = of_n_size_cells(np);
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/* Get parent address wide wide */
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paw = of_n_addr_cells(np);
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range_start = of_read_number(dt_range + aw, paw);
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range_size = of_read_number(dt_range + aw + paw, sw);
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dev_info(&dev->dev, "%s: LAW start 0x%016llx, size 0x%016llx.\n",
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np->full_name, range_start, range_size);
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port = kzalloc(sizeof(struct rio_mport), GFP_KERNEL);
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if (!port)
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continue;
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i = *port_index - 1;
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port->index = (unsigned char)i;
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priv = kzalloc(sizeof(struct rio_priv), GFP_KERNEL);
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if (!priv) {
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dev_err(&dev->dev, "Can't alloc memory for 'priv'\n");
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kfree(port);
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continue;
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}
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INIT_LIST_HEAD(&port->dbells);
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port->iores.start = range_start;
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port->iores.end = port->iores.start + range_size - 1;
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port->iores.flags = IORESOURCE_MEM;
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port->iores.name = "rio_io_win";
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if (request_resource(&iomem_resource, &port->iores) < 0) {
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dev_err(&dev->dev, "RIO: Error requesting master port region"
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" 0x%016llx-0x%016llx\n",
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(u64)port->iores.start, (u64)port->iores.end);
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kfree(priv);
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kfree(port);
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continue;
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}
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sprintf(port->name, "RIO mport %d", i);
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priv->dev = &dev->dev;
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port->dev.parent = &dev->dev;
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port->ops = ops;
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port->priv = priv;
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port->phys_efptr = 0x100;
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priv->regs_win = rio_regs_win;
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/* Probe the master port phy type */
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ccsr = in_be32(priv->regs_win + RIO_CCSR + i*0x20);
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port->phy_type = (ccsr & 1) ? RIO_PHY_SERIAL : RIO_PHY_PARALLEL;
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if (port->phy_type == RIO_PHY_PARALLEL) {
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dev_err(&dev->dev, "RIO: Parallel PHY type, unsupported port type!\n");
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release_resource(&port->iores);
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kfree(priv);
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kfree(port);
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continue;
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}
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dev_info(&dev->dev, "RapidIO PHY type: Serial\n");
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/* Checking the port training status */
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if (in_be32((priv->regs_win + RIO_ESCSR + i*0x20)) & 1) {
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dev_err(&dev->dev, "Port %d is not ready. "
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"Try to restart connection...\n", i);
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/* Disable ports */
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out_be32(priv->regs_win
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+ RIO_CCSR + i*0x20, 0);
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/* Set 1x lane */
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setbits32(priv->regs_win
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+ RIO_CCSR + i*0x20, 0x02000000);
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/* Enable ports */
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setbits32(priv->regs_win
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+ RIO_CCSR + i*0x20, 0x00600000);
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msleep(100);
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if (in_be32((priv->regs_win
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+ RIO_ESCSR + i*0x20)) & 1) {
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dev_err(&dev->dev,
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"Port %d restart failed.\n", i);
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release_resource(&port->iores);
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kfree(priv);
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kfree(port);
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continue;
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}
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dev_info(&dev->dev, "Port %d restart success!\n", i);
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}
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fsl_rio_info(&dev->dev, ccsr);
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port->sys_size = (in_be32((priv->regs_win + RIO_PEF_CAR))
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& RIO_PEF_CTLS) >> 4;
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dev_info(&dev->dev, "RapidIO Common Transport System size: %d\n",
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port->sys_size ? 65536 : 256);
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if (rio_register_mport(port)) {
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release_resource(&port->iores);
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kfree(priv);
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kfree(port);
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continue;
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}
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if (port->host_deviceid >= 0)
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out_be32(priv->regs_win + RIO_GCCSR, RIO_PORT_GEN_HOST |
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RIO_PORT_GEN_MASTER | RIO_PORT_GEN_DISCOVERED);
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else
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out_be32(priv->regs_win + RIO_GCCSR,
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RIO_PORT_GEN_MASTER);
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priv->atmu_regs = (struct rio_atmu_regs *)(priv->regs_win
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+ ((i == 0) ? RIO_ATMU_REGS_PORT1_OFFSET :
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RIO_ATMU_REGS_PORT2_OFFSET));
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priv->maint_atmu_regs = priv->atmu_regs + 1;
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priv->inb_atmu_regs = (struct rio_inb_atmu_regs __iomem *)
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(priv->regs_win +
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((i == 0) ? RIO_INB_ATMU_REGS_PORT1_OFFSET :
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RIO_INB_ATMU_REGS_PORT2_OFFSET));
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/* Set to receive any dist ID for serial RapidIO controller. */
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if (port->phy_type == RIO_PHY_SERIAL)
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out_be32((priv->regs_win
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+ RIO_ISR_AACR + i*0x80), RIO_ISR_AACR_AA);
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/* Configure maintenance transaction window */
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out_be32(&priv->maint_atmu_regs->rowbar,
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port->iores.start >> 12);
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out_be32(&priv->maint_atmu_regs->rowar,
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0x80077000 | (ilog2(RIO_MAINT_WIN_SIZE) - 1));
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priv->maint_win = ioremap(port->iores.start,
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RIO_MAINT_WIN_SIZE);
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rio_law_start = range_start;
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fsl_rio_setup_rmu(port, rmu_np[i]);
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fsl_rio_inbound_mem_init(priv);
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dbell->mport[i] = port;
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|
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active_ports++;
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}
|
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|
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if (!active_ports) {
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rc = -ENOLINK;
|
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goto err;
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}
|
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|
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fsl_rio_doorbell_init(dbell);
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fsl_rio_port_write_init(pw);
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return 0;
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err:
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kfree(pw);
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pw = NULL;
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err_pw:
|
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kfree(dbell);
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dbell = NULL;
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err_dbell:
|
|
iounmap(rmu_regs_win);
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rmu_regs_win = NULL;
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err_rmu:
|
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kfree(ops);
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err_ops:
|
|
iounmap(rio_regs_win);
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rio_regs_win = NULL;
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err_rio_regs:
|
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return rc;
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}
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|
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/* The probe function for RapidIO peer-to-peer network.
|
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*/
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static int fsl_of_rio_rpn_probe(struct platform_device *dev)
|
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{
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printk(KERN_INFO "Setting up RapidIO peer-to-peer network %s\n",
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dev->dev.of_node->full_name);
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return fsl_rio_setup(dev);
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};
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|
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static const struct of_device_id fsl_of_rio_rpn_ids[] = {
|
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{
|
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.compatible = "fsl,srio",
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},
|
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{},
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};
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|
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static struct platform_driver fsl_of_rio_rpn_driver = {
|
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.driver = {
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.name = "fsl-of-rio",
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.of_match_table = fsl_of_rio_rpn_ids,
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},
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.probe = fsl_of_rio_rpn_probe,
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};
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|
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static __init int fsl_of_rio_rpn_init(void)
|
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{
|
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return platform_driver_register(&fsl_of_rio_rpn_driver);
|
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}
|
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|
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subsys_initcall(fsl_of_rio_rpn_init);
|