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dec85a9516
With the board file support gone, and the platform using DT only, a lot of the remaining code is no longer referenced and can be removed. Technically, the DT file only references DA850, but since that is very similar to DA830, I'm leaving the latter. Acked-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
70 lines
2.1 KiB
C
70 lines
2.1 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* DA8XX/OMAP L1XX platform device data
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*
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* Copyright (c) 2007-2009, MontaVista Software, Inc. <source@mvista.com>
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* Derived from code that was:
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* Copyright (C) 2006 Komal Shah <komal_shah802003@yahoo.com>
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*/
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#include <linux/ahci_platform.h>
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#include <linux/clk-provider.h>
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#include <linux/clk.h>
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#include <linux/clkdev.h>
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#include <linux/dma-map-ops.h>
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#include <linux/dmaengine.h>
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#include <linux/init.h>
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#include <linux/io.h>
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#include <linux/platform_device.h>
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#include <linux/reboot.h>
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#include <linux/serial_8250.h>
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#include "common.h"
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#include "cputype.h"
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#include "da8xx.h"
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#include "cpuidle.h"
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#include "irqs.h"
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#include "sram.h"
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#define DA8XX_TPCC_BASE 0x01c00000
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#define DA8XX_TPTC0_BASE 0x01c08000
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#define DA8XX_TPTC1_BASE 0x01c08400
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#define DA8XX_WDOG_BASE 0x01c21000 /* DA8XX_TIMER64P1_BASE */
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#define DA8XX_I2C0_BASE 0x01c22000
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#define DA8XX_RTC_BASE 0x01c23000
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#define DA8XX_PRUSS_MEM_BASE 0x01c30000
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#define DA8XX_MMCSD0_BASE 0x01c40000
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#define DA8XX_SPI0_BASE 0x01c41000
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#define DA830_SPI1_BASE 0x01e12000
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#define DA8XX_LCD_CNTRL_BASE 0x01e13000
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#define DA850_SATA_BASE 0x01e18000
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#define DA850_MMCSD1_BASE 0x01e1b000
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#define DA8XX_EMAC_CPPI_PORT_BASE 0x01e20000
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#define DA8XX_EMAC_CPGMACSS_BASE 0x01e22000
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#define DA8XX_EMAC_CPGMAC_BASE 0x01e23000
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#define DA8XX_EMAC_MDIO_BASE 0x01e24000
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#define DA8XX_I2C1_BASE 0x01e28000
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#define DA850_TPCC1_BASE 0x01e30000
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#define DA850_TPTC2_BASE 0x01e38000
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#define DA850_SPI1_BASE 0x01f0e000
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#define DA8XX_DDR2_CTL_BASE 0xb0000000
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#define DA8XX_EMAC_CTRL_REG_OFFSET 0x3000
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#define DA8XX_EMAC_MOD_REG_OFFSET 0x2000
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#define DA8XX_EMAC_RAM_OFFSET 0x0000
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#define DA8XX_EMAC_CTRL_RAM_SIZE SZ_8K
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void __iomem *da8xx_syscfg0_base;
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void __iomem *da8xx_syscfg1_base;
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static void __iomem *da8xx_ddr2_ctlr_base;
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void __iomem * __init da8xx_get_mem_ctlr(void)
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{
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if (da8xx_ddr2_ctlr_base)
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return da8xx_ddr2_ctlr_base;
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da8xx_ddr2_ctlr_base = ioremap(DA8XX_DDR2_CTL_BASE, SZ_32K);
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if (!da8xx_ddr2_ctlr_base)
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pr_warn("%s: Unable to map DDR2 controller", __func__);
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return da8xx_ddr2_ctlr_base;
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}
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