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![Chunyan Zhang](/assets/img/avatar_default.png)
This patch introduced composite driver for Spreadtrum's SoCs. The functions of this composite clock simply consist of divider and mux clocks. Signed-off-by: Chunyan Zhang <chunyan.zhang@spreadtrum.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
60 lines
1.5 KiB
C
60 lines
1.5 KiB
C
// SPDX-License-Identifier: GPL-2.0
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//
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// Spreadtrum composite clock driver
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//
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// Copyright (C) 2017 Spreadtrum, Inc.
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// Author: Chunyan Zhang <chunyan.zhang@spreadtrum.com>
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#include <linux/clk-provider.h>
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#include "composite.h"
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static long sprd_comp_round_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long *parent_rate)
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{
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struct sprd_comp *cc = hw_to_sprd_comp(hw);
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return sprd_div_helper_round_rate(&cc->common, &cc->div,
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rate, parent_rate);
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}
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static unsigned long sprd_comp_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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struct sprd_comp *cc = hw_to_sprd_comp(hw);
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return sprd_div_helper_recalc_rate(&cc->common, &cc->div, parent_rate);
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}
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static int sprd_comp_set_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long parent_rate)
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{
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struct sprd_comp *cc = hw_to_sprd_comp(hw);
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return sprd_div_helper_set_rate(&cc->common, &cc->div,
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rate, parent_rate);
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}
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static u8 sprd_comp_get_parent(struct clk_hw *hw)
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{
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struct sprd_comp *cc = hw_to_sprd_comp(hw);
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return sprd_mux_helper_get_parent(&cc->common, &cc->mux);
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}
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static int sprd_comp_set_parent(struct clk_hw *hw, u8 index)
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{
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struct sprd_comp *cc = hw_to_sprd_comp(hw);
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return sprd_mux_helper_set_parent(&cc->common, &cc->mux, index);
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}
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const struct clk_ops sprd_comp_ops = {
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.get_parent = sprd_comp_get_parent,
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.set_parent = sprd_comp_set_parent,
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.round_rate = sprd_comp_round_rate,
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.recalc_rate = sprd_comp_recalc_rate,
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.set_rate = sprd_comp_set_rate,
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};
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EXPORT_SYMBOL_GPL(sprd_comp_ops);
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