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![Tero Kristo](/assets/img/avatar_default.png)
Currently, TI clock driver uses an encapsulated struct that is cast into a void pointer to store all register addresses. This can be considered as rather nasty hackery, and prevents from expanding the register address field also. Instead, replace all the code to use proper struct in place for this, which contains all the previously used data. This patch is rather large as it is touching multiple files, but this can't be split up as we need to avoid any boot breakage. Signed-off-by: Tero Kristo <t-kristo@ti.com> Acked-by: Tony Lindgren <tony@atomide.com>
907 lines
24 KiB
C
907 lines
24 KiB
C
/*
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* OMAP3/4 - specific DPLL control functions
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*
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* Copyright (C) 2009-2010 Texas Instruments, Inc.
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* Copyright (C) 2009-2010 Nokia Corporation
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*
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* Written by Paul Walmsley
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* Testing and integration fixes by Jouni Högander
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*
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* 36xx support added by Vishwanath BS, Richard Woodruff, and Nishanth
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* Menon
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*
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* Parts of this code are based on code written by
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* Richard Woodruff, Tony Lindgren, Tuukka Tikkanen, Karthik Dasu
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/kernel.h>
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#include <linux/device.h>
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#include <linux/list.h>
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#include <linux/errno.h>
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#include <linux/delay.h>
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#include <linux/clk.h>
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#include <linux/io.h>
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#include <linux/bitops.h>
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#include <linux/clkdev.h>
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#include <linux/clk/ti.h>
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#include "clock.h"
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/* CM_AUTOIDLE_PLL*.AUTO_* bit values */
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#define DPLL_AUTOIDLE_DISABLE 0x0
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#define DPLL_AUTOIDLE_LOW_POWER_STOP 0x1
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#define MAX_DPLL_WAIT_TRIES 1000000
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#define OMAP3XXX_EN_DPLL_LOCKED 0x7
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/* Forward declarations */
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static u32 omap3_dpll_autoidle_read(struct clk_hw_omap *clk);
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static void omap3_dpll_deny_idle(struct clk_hw_omap *clk);
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static void omap3_dpll_allow_idle(struct clk_hw_omap *clk);
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/* Private functions */
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/* _omap3_dpll_write_clken - write clken_bits arg to a DPLL's enable bits */
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static void _omap3_dpll_write_clken(struct clk_hw_omap *clk, u8 clken_bits)
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{
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const struct dpll_data *dd;
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u32 v;
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dd = clk->dpll_data;
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v = ti_clk_ll_ops->clk_readl(&dd->control_reg);
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v &= ~dd->enable_mask;
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v |= clken_bits << __ffs(dd->enable_mask);
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ti_clk_ll_ops->clk_writel(v, &dd->control_reg);
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}
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/* _omap3_wait_dpll_status: wait for a DPLL to enter a specific state */
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static int _omap3_wait_dpll_status(struct clk_hw_omap *clk, u8 state)
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{
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const struct dpll_data *dd;
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int i = 0;
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int ret = -EINVAL;
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const char *clk_name;
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dd = clk->dpll_data;
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clk_name = clk_hw_get_name(&clk->hw);
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state <<= __ffs(dd->idlest_mask);
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while (((ti_clk_ll_ops->clk_readl(&dd->idlest_reg) & dd->idlest_mask)
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!= state) && i < MAX_DPLL_WAIT_TRIES) {
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i++;
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udelay(1);
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}
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if (i == MAX_DPLL_WAIT_TRIES) {
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pr_err("clock: %s failed transition to '%s'\n",
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clk_name, (state) ? "locked" : "bypassed");
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} else {
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pr_debug("clock: %s transition to '%s' in %d loops\n",
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clk_name, (state) ? "locked" : "bypassed", i);
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ret = 0;
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}
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return ret;
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}
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/* From 3430 TRM ES2 4.7.6.2 */
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static u16 _omap3_dpll_compute_freqsel(struct clk_hw_omap *clk, u8 n)
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{
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unsigned long fint;
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u16 f = 0;
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fint = clk_hw_get_rate(clk->dpll_data->clk_ref) / n;
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pr_debug("clock: fint is %lu\n", fint);
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if (fint >= 750000 && fint <= 1000000)
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f = 0x3;
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else if (fint > 1000000 && fint <= 1250000)
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f = 0x4;
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else if (fint > 1250000 && fint <= 1500000)
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f = 0x5;
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else if (fint > 1500000 && fint <= 1750000)
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f = 0x6;
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else if (fint > 1750000 && fint <= 2100000)
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f = 0x7;
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else if (fint > 7500000 && fint <= 10000000)
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f = 0xB;
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else if (fint > 10000000 && fint <= 12500000)
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f = 0xC;
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else if (fint > 12500000 && fint <= 15000000)
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f = 0xD;
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else if (fint > 15000000 && fint <= 17500000)
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f = 0xE;
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else if (fint > 17500000 && fint <= 21000000)
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f = 0xF;
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else
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pr_debug("clock: unknown freqsel setting for %d\n", n);
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return f;
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}
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/*
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* _omap3_noncore_dpll_lock - instruct a DPLL to lock and wait for readiness
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* @clk: pointer to a DPLL struct clk
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*
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* Instructs a non-CORE DPLL to lock. Waits for the DPLL to report
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* readiness before returning. Will save and restore the DPLL's
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* autoidle state across the enable, per the CDP code. If the DPLL
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* locked successfully, return 0; if the DPLL did not lock in the time
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* allotted, or DPLL3 was passed in, return -EINVAL.
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*/
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static int _omap3_noncore_dpll_lock(struct clk_hw_omap *clk)
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{
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const struct dpll_data *dd;
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u8 ai;
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u8 state = 1;
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int r = 0;
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pr_debug("clock: locking DPLL %s\n", clk_hw_get_name(&clk->hw));
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dd = clk->dpll_data;
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state <<= __ffs(dd->idlest_mask);
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/* Check if already locked */
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if ((ti_clk_ll_ops->clk_readl(&dd->idlest_reg) & dd->idlest_mask) ==
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state)
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goto done;
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ai = omap3_dpll_autoidle_read(clk);
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if (ai)
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omap3_dpll_deny_idle(clk);
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_omap3_dpll_write_clken(clk, DPLL_LOCKED);
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r = _omap3_wait_dpll_status(clk, 1);
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if (ai)
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omap3_dpll_allow_idle(clk);
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done:
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return r;
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}
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/*
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* _omap3_noncore_dpll_bypass - instruct a DPLL to bypass and wait for readiness
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* @clk: pointer to a DPLL struct clk
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*
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* Instructs a non-CORE DPLL to enter low-power bypass mode. In
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* bypass mode, the DPLL's rate is set equal to its parent clock's
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* rate. Waits for the DPLL to report readiness before returning.
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* Will save and restore the DPLL's autoidle state across the enable,
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* per the CDP code. If the DPLL entered bypass mode successfully,
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* return 0; if the DPLL did not enter bypass in the time allotted, or
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* DPLL3 was passed in, or the DPLL does not support low-power bypass,
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* return -EINVAL.
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*/
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static int _omap3_noncore_dpll_bypass(struct clk_hw_omap *clk)
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{
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int r;
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u8 ai;
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if (!(clk->dpll_data->modes & (1 << DPLL_LOW_POWER_BYPASS)))
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return -EINVAL;
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pr_debug("clock: configuring DPLL %s for low-power bypass\n",
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clk_hw_get_name(&clk->hw));
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ai = omap3_dpll_autoidle_read(clk);
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_omap3_dpll_write_clken(clk, DPLL_LOW_POWER_BYPASS);
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r = _omap3_wait_dpll_status(clk, 0);
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if (ai)
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omap3_dpll_allow_idle(clk);
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return r;
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}
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/*
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* _omap3_noncore_dpll_stop - instruct a DPLL to stop
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* @clk: pointer to a DPLL struct clk
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*
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* Instructs a non-CORE DPLL to enter low-power stop. Will save and
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* restore the DPLL's autoidle state across the stop, per the CDP
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* code. If DPLL3 was passed in, or the DPLL does not support
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* low-power stop, return -EINVAL; otherwise, return 0.
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*/
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static int _omap3_noncore_dpll_stop(struct clk_hw_omap *clk)
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{
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u8 ai;
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if (!(clk->dpll_data->modes & (1 << DPLL_LOW_POWER_STOP)))
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return -EINVAL;
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pr_debug("clock: stopping DPLL %s\n", clk_hw_get_name(&clk->hw));
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ai = omap3_dpll_autoidle_read(clk);
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_omap3_dpll_write_clken(clk, DPLL_LOW_POWER_STOP);
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if (ai)
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omap3_dpll_allow_idle(clk);
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return 0;
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}
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/**
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* _lookup_dco - Lookup DCO used by j-type DPLL
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* @clk: pointer to a DPLL struct clk
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* @dco: digital control oscillator selector
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* @m: DPLL multiplier to set
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* @n: DPLL divider to set
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*
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* See 36xx TRM section 3.5.3.3.3.2 "Type B DPLL (Low-Jitter)"
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*
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* XXX This code is not needed for 3430/AM35xx; can it be optimized
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* out in non-multi-OMAP builds for those chips?
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*/
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static void _lookup_dco(struct clk_hw_omap *clk, u8 *dco, u16 m, u8 n)
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{
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unsigned long fint, clkinp; /* watch out for overflow */
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clkinp = clk_hw_get_rate(clk_hw_get_parent(&clk->hw));
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fint = (clkinp / n) * m;
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if (fint < 1000000000)
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*dco = 2;
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else
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*dco = 4;
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}
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/**
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* _lookup_sddiv - Calculate sigma delta divider for j-type DPLL
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* @clk: pointer to a DPLL struct clk
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* @sd_div: target sigma-delta divider
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* @m: DPLL multiplier to set
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* @n: DPLL divider to set
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*
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* See 36xx TRM section 3.5.3.3.3.2 "Type B DPLL (Low-Jitter)"
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*
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* XXX This code is not needed for 3430/AM35xx; can it be optimized
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* out in non-multi-OMAP builds for those chips?
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*/
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static void _lookup_sddiv(struct clk_hw_omap *clk, u8 *sd_div, u16 m, u8 n)
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{
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unsigned long clkinp, sd; /* watch out for overflow */
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int mod1, mod2;
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clkinp = clk_hw_get_rate(clk_hw_get_parent(&clk->hw));
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/*
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* target sigma-delta to near 250MHz
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* sd = ceil[(m/(n+1)) * (clkinp_MHz / 250)]
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*/
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clkinp /= 100000; /* shift from MHz to 10*Hz for 38.4 and 19.2 */
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mod1 = (clkinp * m) % (250 * n);
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sd = (clkinp * m) / (250 * n);
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mod2 = sd % 10;
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sd /= 10;
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if (mod1 || mod2)
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sd++;
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*sd_div = sd;
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}
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/*
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* _omap3_noncore_dpll_program - set non-core DPLL M,N values directly
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* @clk: struct clk * of DPLL to set
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* @freqsel: FREQSEL value to set
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*
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* Program the DPLL with the last M, N values calculated, and wait for
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* the DPLL to lock. Returns -EINVAL upon error, or 0 upon success.
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*/
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static int omap3_noncore_dpll_program(struct clk_hw_omap *clk, u16 freqsel)
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{
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struct dpll_data *dd = clk->dpll_data;
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u8 dco, sd_div, ai = 0;
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u32 v;
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bool errata_i810;
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/* 3430 ES2 TRM: 4.7.6.9 DPLL Programming Sequence */
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_omap3_noncore_dpll_bypass(clk);
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/*
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* Set jitter correction. Jitter correction applicable for OMAP343X
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* only since freqsel field is no longer present on other devices.
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*/
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if (ti_clk_get_features()->flags & TI_CLK_DPLL_HAS_FREQSEL) {
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v = ti_clk_ll_ops->clk_readl(&dd->control_reg);
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v &= ~dd->freqsel_mask;
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v |= freqsel << __ffs(dd->freqsel_mask);
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ti_clk_ll_ops->clk_writel(v, &dd->control_reg);
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}
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/* Set DPLL multiplier, divider */
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v = ti_clk_ll_ops->clk_readl(&dd->mult_div1_reg);
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/* Handle Duty Cycle Correction */
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if (dd->dcc_mask) {
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if (dd->last_rounded_rate >= dd->dcc_rate)
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v |= dd->dcc_mask; /* Enable DCC */
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else
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v &= ~dd->dcc_mask; /* Disable DCC */
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}
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v &= ~(dd->mult_mask | dd->div1_mask);
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v |= dd->last_rounded_m << __ffs(dd->mult_mask);
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v |= (dd->last_rounded_n - 1) << __ffs(dd->div1_mask);
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/* Configure dco and sd_div for dplls that have these fields */
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if (dd->dco_mask) {
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_lookup_dco(clk, &dco, dd->last_rounded_m, dd->last_rounded_n);
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v &= ~(dd->dco_mask);
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v |= dco << __ffs(dd->dco_mask);
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}
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if (dd->sddiv_mask) {
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_lookup_sddiv(clk, &sd_div, dd->last_rounded_m,
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dd->last_rounded_n);
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v &= ~(dd->sddiv_mask);
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v |= sd_div << __ffs(dd->sddiv_mask);
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}
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/*
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* Errata i810 - DPLL controller can get stuck while transitioning
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* to a power saving state. Software must ensure the DPLL can not
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* transition to a low power state while changing M/N values.
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* Easiest way to accomplish this is to prevent DPLL autoidle
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* before doing the M/N re-program.
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*/
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errata_i810 = ti_clk_get_features()->flags & TI_CLK_ERRATA_I810;
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if (errata_i810) {
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ai = omap3_dpll_autoidle_read(clk);
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if (ai) {
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omap3_dpll_deny_idle(clk);
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/* OCP barrier */
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omap3_dpll_autoidle_read(clk);
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}
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}
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ti_clk_ll_ops->clk_writel(v, &dd->mult_div1_reg);
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/* Set 4X multiplier and low-power mode */
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if (dd->m4xen_mask || dd->lpmode_mask) {
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v = ti_clk_ll_ops->clk_readl(&dd->control_reg);
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if (dd->m4xen_mask) {
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if (dd->last_rounded_m4xen)
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v |= dd->m4xen_mask;
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else
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v &= ~dd->m4xen_mask;
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}
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if (dd->lpmode_mask) {
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if (dd->last_rounded_lpmode)
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v |= dd->lpmode_mask;
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else
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v &= ~dd->lpmode_mask;
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}
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ti_clk_ll_ops->clk_writel(v, &dd->control_reg);
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}
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/* We let the clock framework set the other output dividers later */
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/* REVISIT: Set ramp-up delay? */
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_omap3_noncore_dpll_lock(clk);
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if (errata_i810 && ai)
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omap3_dpll_allow_idle(clk);
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return 0;
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}
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/* Public functions */
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/**
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* omap3_dpll_recalc - recalculate DPLL rate
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* @clk: DPLL struct clk
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*
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* Recalculate and propagate the DPLL rate.
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*/
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unsigned long omap3_dpll_recalc(struct clk_hw *hw, unsigned long parent_rate)
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{
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struct clk_hw_omap *clk = to_clk_hw_omap(hw);
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return omap2_get_dpll_rate(clk);
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}
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/* Non-CORE DPLL (e.g., DPLLs that do not control SDRC) clock functions */
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/**
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* omap3_noncore_dpll_enable - instruct a DPLL to enter bypass or lock mode
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* @clk: pointer to a DPLL struct clk
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*
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* Instructs a non-CORE DPLL to enable, e.g., to enter bypass or lock.
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* The choice of modes depends on the DPLL's programmed rate: if it is
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* the same as the DPLL's parent clock, it will enter bypass;
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* otherwise, it will enter lock. This code will wait for the DPLL to
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* indicate readiness before returning, unless the DPLL takes too long
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* to enter the target state. Intended to be used as the struct clk's
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* enable function. If DPLL3 was passed in, or the DPLL does not
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* support low-power stop, or if the DPLL took too long to enter
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* bypass or lock, return -EINVAL; otherwise, return 0.
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*/
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int omap3_noncore_dpll_enable(struct clk_hw *hw)
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{
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struct clk_hw_omap *clk = to_clk_hw_omap(hw);
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int r;
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struct dpll_data *dd;
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struct clk_hw *parent;
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dd = clk->dpll_data;
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if (!dd)
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return -EINVAL;
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if (clk->clkdm) {
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r = ti_clk_ll_ops->clkdm_clk_enable(clk->clkdm, hw->clk);
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if (r) {
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WARN(1,
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"%s: could not enable %s's clockdomain %s: %d\n",
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__func__, clk_hw_get_name(hw),
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clk->clkdm_name, r);
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return r;
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}
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}
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parent = clk_hw_get_parent(hw);
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if (clk_hw_get_rate(hw) == clk_hw_get_rate(dd->clk_bypass)) {
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WARN_ON(parent != dd->clk_bypass);
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r = _omap3_noncore_dpll_bypass(clk);
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} else {
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WARN_ON(parent != dd->clk_ref);
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r = _omap3_noncore_dpll_lock(clk);
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}
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return r;
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}
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|
|
/**
|
|
* omap3_noncore_dpll_disable - instruct a DPLL to enter low-power stop
|
|
* @clk: pointer to a DPLL struct clk
|
|
*
|
|
* Instructs a non-CORE DPLL to enter low-power stop. This function is
|
|
* intended for use in struct clkops. No return value.
|
|
*/
|
|
void omap3_noncore_dpll_disable(struct clk_hw *hw)
|
|
{
|
|
struct clk_hw_omap *clk = to_clk_hw_omap(hw);
|
|
|
|
_omap3_noncore_dpll_stop(clk);
|
|
if (clk->clkdm)
|
|
ti_clk_ll_ops->clkdm_clk_disable(clk->clkdm, hw->clk);
|
|
}
|
|
|
|
/* Non-CORE DPLL rate set code */
|
|
|
|
/**
|
|
* omap3_noncore_dpll_determine_rate - determine rate for a DPLL
|
|
* @hw: pointer to the clock to determine rate for
|
|
* @req: target rate request
|
|
*
|
|
* Determines which DPLL mode to use for reaching a desired target rate.
|
|
* Checks whether the DPLL shall be in bypass or locked mode, and if
|
|
* locked, calculates the M,N values for the DPLL via round-rate.
|
|
* Returns a 0 on success, negative error value in failure.
|
|
*/
|
|
int omap3_noncore_dpll_determine_rate(struct clk_hw *hw,
|
|
struct clk_rate_request *req)
|
|
{
|
|
struct clk_hw_omap *clk = to_clk_hw_omap(hw);
|
|
struct dpll_data *dd;
|
|
|
|
if (!req->rate)
|
|
return -EINVAL;
|
|
|
|
dd = clk->dpll_data;
|
|
if (!dd)
|
|
return -EINVAL;
|
|
|
|
if (clk_hw_get_rate(dd->clk_bypass) == req->rate &&
|
|
(dd->modes & (1 << DPLL_LOW_POWER_BYPASS))) {
|
|
req->best_parent_hw = dd->clk_bypass;
|
|
} else {
|
|
req->rate = omap2_dpll_round_rate(hw, req->rate,
|
|
&req->best_parent_rate);
|
|
req->best_parent_hw = dd->clk_ref;
|
|
}
|
|
|
|
req->best_parent_rate = req->rate;
|
|
|
|
return 0;
|
|
}
|
|
|
|
/**
|
|
* omap3_noncore_dpll_set_parent - set parent for a DPLL clock
|
|
* @hw: pointer to the clock to set parent for
|
|
* @index: parent index to select
|
|
*
|
|
* Sets parent for a DPLL clock. This sets the DPLL into bypass or
|
|
* locked mode. Returns 0 with success, negative error value otherwise.
|
|
*/
|
|
int omap3_noncore_dpll_set_parent(struct clk_hw *hw, u8 index)
|
|
{
|
|
struct clk_hw_omap *clk = to_clk_hw_omap(hw);
|
|
int ret;
|
|
|
|
if (!hw)
|
|
return -EINVAL;
|
|
|
|
if (index)
|
|
ret = _omap3_noncore_dpll_bypass(clk);
|
|
else
|
|
ret = _omap3_noncore_dpll_lock(clk);
|
|
|
|
return ret;
|
|
}
|
|
|
|
/**
|
|
* omap3_noncore_dpll_set_rate - set rate for a DPLL clock
|
|
* @hw: pointer to the clock to set parent for
|
|
* @rate: target rate for the clock
|
|
* @parent_rate: rate of the parent clock
|
|
*
|
|
* Sets rate for a DPLL clock. First checks if the clock parent is
|
|
* reference clock (in bypass mode, the rate of the clock can't be
|
|
* changed) and proceeds with the rate change operation. Returns 0
|
|
* with success, negative error value otherwise.
|
|
*/
|
|
int omap3_noncore_dpll_set_rate(struct clk_hw *hw, unsigned long rate,
|
|
unsigned long parent_rate)
|
|
{
|
|
struct clk_hw_omap *clk = to_clk_hw_omap(hw);
|
|
struct dpll_data *dd;
|
|
u16 freqsel = 0;
|
|
int ret;
|
|
|
|
if (!hw || !rate)
|
|
return -EINVAL;
|
|
|
|
dd = clk->dpll_data;
|
|
if (!dd)
|
|
return -EINVAL;
|
|
|
|
if (clk_hw_get_parent(hw) != dd->clk_ref)
|
|
return -EINVAL;
|
|
|
|
if (dd->last_rounded_rate == 0)
|
|
return -EINVAL;
|
|
|
|
/* Freqsel is available only on OMAP343X devices */
|
|
if (ti_clk_get_features()->flags & TI_CLK_DPLL_HAS_FREQSEL) {
|
|
freqsel = _omap3_dpll_compute_freqsel(clk, dd->last_rounded_n);
|
|
WARN_ON(!freqsel);
|
|
}
|
|
|
|
pr_debug("%s: %s: set rate: locking rate to %lu.\n", __func__,
|
|
clk_hw_get_name(hw), rate);
|
|
|
|
ret = omap3_noncore_dpll_program(clk, freqsel);
|
|
|
|
return ret;
|
|
}
|
|
|
|
/**
|
|
* omap3_noncore_dpll_set_rate_and_parent - set rate and parent for a DPLL clock
|
|
* @hw: pointer to the clock to set rate and parent for
|
|
* @rate: target rate for the DPLL
|
|
* @parent_rate: clock rate of the DPLL parent
|
|
* @index: new parent index for the DPLL, 0 - reference, 1 - bypass
|
|
*
|
|
* Sets rate and parent for a DPLL clock. If new parent is the bypass
|
|
* clock, only selects the parent. Otherwise proceeds with a rate
|
|
* change, as this will effectively also change the parent as the
|
|
* DPLL is put into locked mode. Returns 0 with success, negative error
|
|
* value otherwise.
|
|
*/
|
|
int omap3_noncore_dpll_set_rate_and_parent(struct clk_hw *hw,
|
|
unsigned long rate,
|
|
unsigned long parent_rate,
|
|
u8 index)
|
|
{
|
|
int ret;
|
|
|
|
if (!hw || !rate)
|
|
return -EINVAL;
|
|
|
|
/*
|
|
* clk-ref at index[0], in which case we only need to set rate,
|
|
* the parent will be changed automatically with the lock sequence.
|
|
* With clk-bypass case we only need to change parent.
|
|
*/
|
|
if (index)
|
|
ret = omap3_noncore_dpll_set_parent(hw, index);
|
|
else
|
|
ret = omap3_noncore_dpll_set_rate(hw, rate, parent_rate);
|
|
|
|
return ret;
|
|
}
|
|
|
|
/* DPLL autoidle read/set code */
|
|
|
|
/**
|
|
* omap3_dpll_autoidle_read - read a DPLL's autoidle bits
|
|
* @clk: struct clk * of the DPLL to read
|
|
*
|
|
* Return the DPLL's autoidle bits, shifted down to bit 0. Returns
|
|
* -EINVAL if passed a null pointer or if the struct clk does not
|
|
* appear to refer to a DPLL.
|
|
*/
|
|
static u32 omap3_dpll_autoidle_read(struct clk_hw_omap *clk)
|
|
{
|
|
const struct dpll_data *dd;
|
|
u32 v;
|
|
|
|
if (!clk || !clk->dpll_data)
|
|
return -EINVAL;
|
|
|
|
dd = clk->dpll_data;
|
|
|
|
if (!dd->autoidle_mask)
|
|
return -EINVAL;
|
|
|
|
v = ti_clk_ll_ops->clk_readl(&dd->autoidle_reg);
|
|
v &= dd->autoidle_mask;
|
|
v >>= __ffs(dd->autoidle_mask);
|
|
|
|
return v;
|
|
}
|
|
|
|
/**
|
|
* omap3_dpll_allow_idle - enable DPLL autoidle bits
|
|
* @clk: struct clk * of the DPLL to operate on
|
|
*
|
|
* Enable DPLL automatic idle control. This automatic idle mode
|
|
* switching takes effect only when the DPLL is locked, at least on
|
|
* OMAP3430. The DPLL will enter low-power stop when its downstream
|
|
* clocks are gated. No return value.
|
|
*/
|
|
static void omap3_dpll_allow_idle(struct clk_hw_omap *clk)
|
|
{
|
|
const struct dpll_data *dd;
|
|
u32 v;
|
|
|
|
if (!clk || !clk->dpll_data)
|
|
return;
|
|
|
|
dd = clk->dpll_data;
|
|
|
|
if (!dd->autoidle_mask)
|
|
return;
|
|
|
|
/*
|
|
* REVISIT: CORE DPLL can optionally enter low-power bypass
|
|
* by writing 0x5 instead of 0x1. Add some mechanism to
|
|
* optionally enter this mode.
|
|
*/
|
|
v = ti_clk_ll_ops->clk_readl(&dd->autoidle_reg);
|
|
v &= ~dd->autoidle_mask;
|
|
v |= DPLL_AUTOIDLE_LOW_POWER_STOP << __ffs(dd->autoidle_mask);
|
|
ti_clk_ll_ops->clk_writel(v, &dd->autoidle_reg);
|
|
}
|
|
|
|
/**
|
|
* omap3_dpll_deny_idle - prevent DPLL from automatically idling
|
|
* @clk: struct clk * of the DPLL to operate on
|
|
*
|
|
* Disable DPLL automatic idle control. No return value.
|
|
*/
|
|
static void omap3_dpll_deny_idle(struct clk_hw_omap *clk)
|
|
{
|
|
const struct dpll_data *dd;
|
|
u32 v;
|
|
|
|
if (!clk || !clk->dpll_data)
|
|
return;
|
|
|
|
dd = clk->dpll_data;
|
|
|
|
if (!dd->autoidle_mask)
|
|
return;
|
|
|
|
v = ti_clk_ll_ops->clk_readl(&dd->autoidle_reg);
|
|
v &= ~dd->autoidle_mask;
|
|
v |= DPLL_AUTOIDLE_DISABLE << __ffs(dd->autoidle_mask);
|
|
ti_clk_ll_ops->clk_writel(v, &dd->autoidle_reg);
|
|
}
|
|
|
|
/* Clock control for DPLL outputs */
|
|
|
|
/* Find the parent DPLL for the given clkoutx2 clock */
|
|
static struct clk_hw_omap *omap3_find_clkoutx2_dpll(struct clk_hw *hw)
|
|
{
|
|
struct clk_hw_omap *pclk = NULL;
|
|
|
|
/* Walk up the parents of clk, looking for a DPLL */
|
|
do {
|
|
do {
|
|
hw = clk_hw_get_parent(hw);
|
|
} while (hw && (clk_hw_get_flags(hw) & CLK_IS_BASIC));
|
|
if (!hw)
|
|
break;
|
|
pclk = to_clk_hw_omap(hw);
|
|
} while (pclk && !pclk->dpll_data);
|
|
|
|
/* clk does not have a DPLL as a parent? error in the clock data */
|
|
if (!pclk) {
|
|
WARN_ON(1);
|
|
return NULL;
|
|
}
|
|
|
|
return pclk;
|
|
}
|
|
|
|
/**
|
|
* omap3_clkoutx2_recalc - recalculate DPLL X2 output virtual clock rate
|
|
* @clk: DPLL output struct clk
|
|
*
|
|
* Using parent clock DPLL data, look up DPLL state. If locked, set our
|
|
* rate to the dpll_clk * 2; otherwise, just use dpll_clk.
|
|
*/
|
|
unsigned long omap3_clkoutx2_recalc(struct clk_hw *hw,
|
|
unsigned long parent_rate)
|
|
{
|
|
const struct dpll_data *dd;
|
|
unsigned long rate;
|
|
u32 v;
|
|
struct clk_hw_omap *pclk = NULL;
|
|
|
|
if (!parent_rate)
|
|
return 0;
|
|
|
|
pclk = omap3_find_clkoutx2_dpll(hw);
|
|
|
|
if (!pclk)
|
|
return 0;
|
|
|
|
dd = pclk->dpll_data;
|
|
|
|
WARN_ON(!dd->enable_mask);
|
|
|
|
v = ti_clk_ll_ops->clk_readl(&dd->control_reg) & dd->enable_mask;
|
|
v >>= __ffs(dd->enable_mask);
|
|
if ((v != OMAP3XXX_EN_DPLL_LOCKED) || (dd->flags & DPLL_J_TYPE))
|
|
rate = parent_rate;
|
|
else
|
|
rate = parent_rate * 2;
|
|
return rate;
|
|
}
|
|
|
|
/* OMAP3/4 non-CORE DPLL clkops */
|
|
const struct clk_hw_omap_ops clkhwops_omap3_dpll = {
|
|
.allow_idle = omap3_dpll_allow_idle,
|
|
.deny_idle = omap3_dpll_deny_idle,
|
|
};
|
|
|
|
/**
|
|
* omap3_dpll4_set_rate - set rate for omap3 per-dpll
|
|
* @hw: clock to change
|
|
* @rate: target rate for clock
|
|
* @parent_rate: rate of the parent clock
|
|
*
|
|
* Check if the current SoC supports the per-dpll reprogram operation
|
|
* or not, and then do the rate change if supported. Returns -EINVAL
|
|
* if not supported, 0 for success, and potential error codes from the
|
|
* clock rate change.
|
|
*/
|
|
int omap3_dpll4_set_rate(struct clk_hw *hw, unsigned long rate,
|
|
unsigned long parent_rate)
|
|
{
|
|
/*
|
|
* According to the 12-5 CDP code from TI, "Limitation 2.5"
|
|
* on 3430ES1 prevents us from changing DPLL multipliers or dividers
|
|
* on DPLL4.
|
|
*/
|
|
if (ti_clk_get_features()->flags & TI_CLK_DPLL4_DENY_REPROGRAM) {
|
|
pr_err("clock: DPLL4 cannot change rate due to silicon 'Limitation 2.5' on 3430ES1.\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
return omap3_noncore_dpll_set_rate(hw, rate, parent_rate);
|
|
}
|
|
|
|
/**
|
|
* omap3_dpll4_set_rate_and_parent - set rate and parent for omap3 per-dpll
|
|
* @hw: clock to change
|
|
* @rate: target rate for clock
|
|
* @parent_rate: rate of the parent clock
|
|
* @index: parent index, 0 - reference clock, 1 - bypass clock
|
|
*
|
|
* Check if the current SoC support the per-dpll reprogram operation
|
|
* or not, and then do the rate + parent change if supported. Returns
|
|
* -EINVAL if not supported, 0 for success, and potential error codes
|
|
* from the clock rate change.
|
|
*/
|
|
int omap3_dpll4_set_rate_and_parent(struct clk_hw *hw, unsigned long rate,
|
|
unsigned long parent_rate, u8 index)
|
|
{
|
|
if (ti_clk_get_features()->flags & TI_CLK_DPLL4_DENY_REPROGRAM) {
|
|
pr_err("clock: DPLL4 cannot change rate due to silicon 'Limitation 2.5' on 3430ES1.\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
return omap3_noncore_dpll_set_rate_and_parent(hw, rate, parent_rate,
|
|
index);
|
|
}
|
|
|
|
/* Apply DM3730 errata sprz319 advisory 2.1. */
|
|
static bool omap3_dpll5_apply_errata(struct clk_hw *hw,
|
|
unsigned long parent_rate)
|
|
{
|
|
struct omap3_dpll5_settings {
|
|
unsigned int rate, m, n;
|
|
};
|
|
|
|
static const struct omap3_dpll5_settings precomputed[] = {
|
|
/*
|
|
* From DM3730 errata advisory 2.1, table 35 and 36.
|
|
* The N value is increased by 1 compared to the tables as the
|
|
* errata lists register values while last_rounded_field is the
|
|
* real divider value.
|
|
*/
|
|
{ 12000000, 80, 0 + 1 },
|
|
{ 13000000, 443, 5 + 1 },
|
|
{ 19200000, 50, 0 + 1 },
|
|
{ 26000000, 443, 11 + 1 },
|
|
{ 38400000, 25, 0 + 1 }
|
|
};
|
|
|
|
const struct omap3_dpll5_settings *d;
|
|
struct clk_hw_omap *clk = to_clk_hw_omap(hw);
|
|
struct dpll_data *dd;
|
|
unsigned int i;
|
|
|
|
for (i = 0; i < ARRAY_SIZE(precomputed); ++i) {
|
|
if (parent_rate == precomputed[i].rate)
|
|
break;
|
|
}
|
|
|
|
if (i == ARRAY_SIZE(precomputed))
|
|
return false;
|
|
|
|
d = &precomputed[i];
|
|
|
|
/* Update the M, N and rounded rate values and program the DPLL. */
|
|
dd = clk->dpll_data;
|
|
dd->last_rounded_m = d->m;
|
|
dd->last_rounded_n = d->n;
|
|
dd->last_rounded_rate = div_u64((u64)parent_rate * d->m, d->n);
|
|
omap3_noncore_dpll_program(clk, 0);
|
|
|
|
return true;
|
|
}
|
|
|
|
/**
|
|
* omap3_dpll5_set_rate - set rate for omap3 dpll5
|
|
* @hw: clock to change
|
|
* @rate: target rate for clock
|
|
* @parent_rate: rate of the parent clock
|
|
*
|
|
* Set rate for the DPLL5 clock. Apply the sprz319 advisory 2.1 on OMAP36xx if
|
|
* the DPLL is used for USB host (detected through the requested rate).
|
|
*/
|
|
int omap3_dpll5_set_rate(struct clk_hw *hw, unsigned long rate,
|
|
unsigned long parent_rate)
|
|
{
|
|
if (rate == OMAP3_DPLL5_FREQ_FOR_USBHOST * 8) {
|
|
if (omap3_dpll5_apply_errata(hw, parent_rate))
|
|
return 0;
|
|
}
|
|
|
|
return omap3_noncore_dpll_set_rate(hw, rate, parent_rate);
|
|
}
|