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![Markus Elfring](/assets/img/avatar_default.png)
Replace the specification of a data structure by a pointer dereference as the parameter for the operator "sizeof" to make the corresponding size determination a bit safer according to the Linux coding style convention. This issue was detected by using the Coccinelle software. Signed-off-by: Markus Elfring <elfring@users.sourceforge.net> Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
578 lines
16 KiB
C
578 lines
16 KiB
C
/*
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* Driver for the ICST307 VCO clock found in the ARM Reference designs.
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* We wrap the custom interface from <asm/hardware/icst.h> into the generic
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* clock framework.
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*
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* Copyright (C) 2012-2015 Linus Walleij
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* TODO: when all ARM reference designs are migrated to generic clocks, the
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* ICST clock code from the ARM tree should probably be merged into this
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* file.
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*/
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#include <linux/kernel.h>
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#include <linux/slab.h>
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#include <linux/export.h>
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#include <linux/err.h>
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#include <linux/clk-provider.h>
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#include <linux/io.h>
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#include <linux/regmap.h>
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#include <linux/mfd/syscon.h>
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#include "icst.h"
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#include "clk-icst.h"
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/* Magic unlocking token used on all Versatile boards */
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#define VERSATILE_LOCK_VAL 0xA05F
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#define VERSATILE_AUX_OSC_BITS 0x7FFFF
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#define INTEGRATOR_AP_CM_BITS 0xFF
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#define INTEGRATOR_AP_SYS_BITS 0xFF
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#define INTEGRATOR_CP_CM_CORE_BITS 0x7FF
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#define INTEGRATOR_CP_CM_MEM_BITS 0x7FF000
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#define INTEGRATOR_AP_PCI_25_33_MHZ BIT(8)
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/**
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* enum icst_control_type - the type of ICST control register
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*/
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enum icst_control_type {
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ICST_VERSATILE, /* The standard type, all control bits available */
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ICST_INTEGRATOR_AP_CM, /* Only 8 bits of VDW available */
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ICST_INTEGRATOR_AP_SYS, /* Only 8 bits of VDW available */
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ICST_INTEGRATOR_AP_PCI, /* Odd bit pattern storage */
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ICST_INTEGRATOR_CP_CM_CORE, /* Only 8 bits of VDW and 3 bits of OD */
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ICST_INTEGRATOR_CP_CM_MEM, /* Only 8 bits of VDW and 3 bits of OD */
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};
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/**
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* struct clk_icst - ICST VCO clock wrapper
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* @hw: corresponding clock hardware entry
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* @vcoreg: VCO register address
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* @lockreg: VCO lock register address
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* @params: parameters for this ICST instance
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* @rate: current rate
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* @ctype: the type of control register for the ICST
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*/
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struct clk_icst {
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struct clk_hw hw;
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struct regmap *map;
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u32 vcoreg_off;
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u32 lockreg_off;
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struct icst_params *params;
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unsigned long rate;
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enum icst_control_type ctype;
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};
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#define to_icst(_hw) container_of(_hw, struct clk_icst, hw)
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/**
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* vco_get() - get ICST VCO settings from a certain ICST
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* @icst: the ICST clock to get
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* @vco: the VCO struct to return the value in
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*/
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static int vco_get(struct clk_icst *icst, struct icst_vco *vco)
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{
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u32 val;
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int ret;
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ret = regmap_read(icst->map, icst->vcoreg_off, &val);
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if (ret)
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return ret;
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/*
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* The Integrator/AP core clock can only access the low eight
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* bits of the v PLL divider. Bit 8 is tied low and always zero,
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* r is hardwired to 22 and output divider s is hardwired to 1
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* (divide by 2) according to the document
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* "Integrator CM926EJ-S, CM946E-S, CM966E-S, CM1026EJ-S and
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* CM1136JF-S User Guide" ARM DUI 0138E, page 3-13 thru 3-14.
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*/
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if (icst->ctype == ICST_INTEGRATOR_AP_CM) {
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vco->v = val & INTEGRATOR_AP_CM_BITS;
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vco->r = 22;
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vco->s = 1;
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return 0;
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}
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/*
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* The Integrator/AP system clock on the base board can only
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* access the low eight bits of the v PLL divider. Bit 8 is tied low
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* and always zero, r is hardwired to 46, and the output divider is
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* hardwired to 3 (divide by 4) according to the document
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* "Integrator AP ASIC Development Motherboard" ARM DUI 0098B,
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* page 3-16.
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*/
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if (icst->ctype == ICST_INTEGRATOR_AP_SYS) {
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vco->v = val & INTEGRATOR_AP_SYS_BITS;
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vco->r = 46;
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vco->s = 3;
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return 0;
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}
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/*
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* The Integrator/AP PCI clock is using an odd pattern to create
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* the child clock, basically a single bit called DIVX/Y is used
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* to select between two different hardwired values: setting the
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* bit to 0 yields v = 17, r = 22 and OD = 1, whereas setting the
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* bit to 1 yields v = 14, r = 14 and OD = 1 giving the frequencies
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* 33 or 25 MHz respectively.
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*/
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if (icst->ctype == ICST_INTEGRATOR_AP_PCI) {
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bool divxy = !!(val & INTEGRATOR_AP_PCI_25_33_MHZ);
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vco->v = divxy ? 17 : 14;
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vco->r = divxy ? 22 : 14;
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vco->s = 1;
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return 0;
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}
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/*
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* The Integrator/CP core clock can access the low eight bits
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* of the v PLL divider. Bit 8 is tied low and always zero,
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* r is hardwired to 22 and the output divider s is accessible
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* in bits 8 thru 10 according to the document
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* "Integrator/CM940T, CM920T, CM740T, and CM720T User Guide"
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* ARM DUI 0157A, page 3-20 thru 3-23 and 4-10.
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*/
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if (icst->ctype == ICST_INTEGRATOR_CP_CM_CORE) {
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vco->v = val & 0xFF;
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vco->r = 22;
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vco->s = (val >> 8) & 7;
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return 0;
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}
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if (icst->ctype == ICST_INTEGRATOR_CP_CM_MEM) {
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vco->v = (val >> 12) & 0xFF;
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vco->r = 22;
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vco->s = (val >> 20) & 7;
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return 0;
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}
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vco->v = val & 0x1ff;
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vco->r = (val >> 9) & 0x7f;
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vco->s = (val >> 16) & 03;
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return 0;
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}
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/**
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* vco_set() - commit changes to an ICST VCO
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* @icst: the ICST clock to set
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* @vco: the VCO struct to set the changes from
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*/
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static int vco_set(struct clk_icst *icst, struct icst_vco vco)
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{
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u32 mask;
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u32 val;
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int ret;
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/* Mask the bits used by the VCO */
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switch (icst->ctype) {
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case ICST_INTEGRATOR_AP_CM:
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mask = INTEGRATOR_AP_CM_BITS;
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val = vco.v & 0xFF;
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if (vco.v & 0x100)
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pr_err("ICST error: tried to set bit 8 of VDW\n");
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if (vco.s != 1)
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pr_err("ICST error: tried to use VOD != 1\n");
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if (vco.r != 22)
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pr_err("ICST error: tried to use RDW != 22\n");
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break;
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case ICST_INTEGRATOR_AP_SYS:
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mask = INTEGRATOR_AP_SYS_BITS;
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val = vco.v & 0xFF;
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if (vco.v & 0x100)
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pr_err("ICST error: tried to set bit 8 of VDW\n");
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if (vco.s != 3)
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pr_err("ICST error: tried to use VOD != 1\n");
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if (vco.r != 46)
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pr_err("ICST error: tried to use RDW != 22\n");
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break;
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case ICST_INTEGRATOR_CP_CM_CORE:
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mask = INTEGRATOR_CP_CM_CORE_BITS; /* Uses 12 bits */
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val = (vco.v & 0xFF) | vco.s << 8;
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if (vco.v & 0x100)
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pr_err("ICST error: tried to set bit 8 of VDW\n");
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if (vco.r != 22)
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pr_err("ICST error: tried to use RDW != 22\n");
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break;
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case ICST_INTEGRATOR_CP_CM_MEM:
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mask = INTEGRATOR_CP_CM_MEM_BITS; /* Uses 12 bits */
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val = ((vco.v & 0xFF) << 12) | (vco.s << 20);
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if (vco.v & 0x100)
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pr_err("ICST error: tried to set bit 8 of VDW\n");
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if (vco.r != 22)
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pr_err("ICST error: tried to use RDW != 22\n");
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break;
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default:
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/* Regular auxilary oscillator */
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mask = VERSATILE_AUX_OSC_BITS;
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val = vco.v | (vco.r << 9) | (vco.s << 16);
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break;
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}
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pr_debug("ICST: new val = 0x%08x\n", val);
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/* This magic unlocks the VCO so it can be controlled */
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ret = regmap_write(icst->map, icst->lockreg_off, VERSATILE_LOCK_VAL);
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if (ret)
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return ret;
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ret = regmap_update_bits(icst->map, icst->vcoreg_off, mask, val);
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if (ret)
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return ret;
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/* This locks the VCO again */
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ret = regmap_write(icst->map, icst->lockreg_off, 0);
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if (ret)
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return ret;
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return 0;
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}
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static unsigned long icst_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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struct clk_icst *icst = to_icst(hw);
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struct icst_vco vco;
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int ret;
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if (parent_rate)
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icst->params->ref = parent_rate;
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ret = vco_get(icst, &vco);
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if (ret) {
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pr_err("ICST: could not get VCO setting\n");
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return 0;
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}
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icst->rate = icst_hz(icst->params, vco);
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return icst->rate;
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}
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static long icst_round_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long *prate)
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{
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struct clk_icst *icst = to_icst(hw);
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struct icst_vco vco;
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if (icst->ctype == ICST_INTEGRATOR_AP_CM ||
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icst->ctype == ICST_INTEGRATOR_CP_CM_CORE) {
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if (rate <= 12000000)
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return 12000000;
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if (rate >= 160000000)
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return 160000000;
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/* Slam to closest megahertz */
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return DIV_ROUND_CLOSEST(rate, 1000000) * 1000000;
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}
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if (icst->ctype == ICST_INTEGRATOR_CP_CM_MEM) {
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if (rate <= 6000000)
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return 6000000;
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if (rate >= 66000000)
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return 66000000;
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/* Slam to closest 0.5 megahertz */
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return DIV_ROUND_CLOSEST(rate, 500000) * 500000;
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}
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if (icst->ctype == ICST_INTEGRATOR_AP_SYS) {
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/* Divides between 3 and 50 MHz in steps of 0.25 MHz */
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if (rate <= 3000000)
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return 3000000;
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if (rate >= 50000000)
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return 5000000;
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/* Slam to closest 0.25 MHz */
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return DIV_ROUND_CLOSEST(rate, 250000) * 250000;
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}
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if (icst->ctype == ICST_INTEGRATOR_AP_PCI) {
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/*
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* If we're below or less than halfway from 25 to 33 MHz
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* select 25 MHz
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*/
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if (rate <= 25000000 || rate < 29000000)
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return 25000000;
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/* Else just return the default frequency */
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return 33000000;
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}
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vco = icst_hz_to_vco(icst->params, rate);
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return icst_hz(icst->params, vco);
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}
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static int icst_set_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long parent_rate)
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{
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struct clk_icst *icst = to_icst(hw);
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struct icst_vco vco;
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if (icst->ctype == ICST_INTEGRATOR_AP_PCI) {
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/* This clock is especially primitive */
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unsigned int val;
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int ret;
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if (rate == 25000000) {
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val = 0;
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} else if (rate == 33000000) {
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val = INTEGRATOR_AP_PCI_25_33_MHZ;
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} else {
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pr_err("ICST: cannot set PCI frequency %lu\n",
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rate);
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return -EINVAL;
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}
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ret = regmap_write(icst->map, icst->lockreg_off,
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VERSATILE_LOCK_VAL);
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if (ret)
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return ret;
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ret = regmap_update_bits(icst->map, icst->vcoreg_off,
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INTEGRATOR_AP_PCI_25_33_MHZ,
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val);
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if (ret)
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return ret;
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/* This locks the VCO again */
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ret = regmap_write(icst->map, icst->lockreg_off, 0);
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if (ret)
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return ret;
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return 0;
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}
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if (parent_rate)
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icst->params->ref = parent_rate;
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vco = icst_hz_to_vco(icst->params, rate);
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icst->rate = icst_hz(icst->params, vco);
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return vco_set(icst, vco);
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}
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static const struct clk_ops icst_ops = {
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.recalc_rate = icst_recalc_rate,
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.round_rate = icst_round_rate,
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.set_rate = icst_set_rate,
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};
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static struct clk *icst_clk_setup(struct device *dev,
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const struct clk_icst_desc *desc,
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const char *name,
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const char *parent_name,
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struct regmap *map,
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enum icst_control_type ctype)
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{
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struct clk *clk;
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struct clk_icst *icst;
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struct clk_init_data init;
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struct icst_params *pclone;
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icst = kzalloc(sizeof(*icst), GFP_KERNEL);
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if (!icst)
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return ERR_PTR(-ENOMEM);
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pclone = kmemdup(desc->params, sizeof(*pclone), GFP_KERNEL);
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if (!pclone) {
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kfree(icst);
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return ERR_PTR(-ENOMEM);
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}
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init.name = name;
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init.ops = &icst_ops;
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init.flags = 0;
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init.parent_names = (parent_name ? &parent_name : NULL);
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init.num_parents = (parent_name ? 1 : 0);
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icst->map = map;
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icst->hw.init = &init;
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icst->params = pclone;
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icst->vcoreg_off = desc->vco_offset;
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icst->lockreg_off = desc->lock_offset;
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icst->ctype = ctype;
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clk = clk_register(dev, &icst->hw);
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if (IS_ERR(clk)) {
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kfree(pclone);
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kfree(icst);
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}
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return clk;
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}
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struct clk *icst_clk_register(struct device *dev,
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const struct clk_icst_desc *desc,
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const char *name,
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const char *parent_name,
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void __iomem *base)
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{
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struct regmap_config icst_regmap_conf = {
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.reg_bits = 32,
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.val_bits = 32,
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.reg_stride = 4,
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};
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struct regmap *map;
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map = regmap_init_mmio(dev, base, &icst_regmap_conf);
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if (IS_ERR(map)) {
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pr_err("could not initialize ICST regmap\n");
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return ERR_CAST(map);
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}
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return icst_clk_setup(dev, desc, name, parent_name, map,
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ICST_VERSATILE);
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}
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EXPORT_SYMBOL_GPL(icst_clk_register);
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#ifdef CONFIG_OF
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/*
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* In a device tree, an memory-mapped ICST clock appear as a child
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* of a syscon node. Assume this and probe it only as a child of a
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* syscon.
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*/
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static const struct icst_params icst525_params = {
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.vco_max = ICST525_VCO_MAX_5V,
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.vco_min = ICST525_VCO_MIN,
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.vd_min = 8,
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.vd_max = 263,
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.rd_min = 3,
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.rd_max = 65,
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.s2div = icst525_s2div,
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.idx2s = icst525_idx2s,
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};
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static const struct icst_params icst307_params = {
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.vco_max = ICST307_VCO_MAX,
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.vco_min = ICST307_VCO_MIN,
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.vd_min = 4 + 8,
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.vd_max = 511 + 8,
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.rd_min = 1 + 2,
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.rd_max = 127 + 2,
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.s2div = icst307_s2div,
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.idx2s = icst307_idx2s,
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};
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/**
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* The core modules on the Integrator/AP and Integrator/CP have
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* especially crippled ICST525 control.
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*/
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static const struct icst_params icst525_apcp_cm_params = {
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.vco_max = ICST525_VCO_MAX_5V,
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.vco_min = ICST525_VCO_MIN,
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/* Minimum 12 MHz, VDW = 4 */
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.vd_min = 12,
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/*
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* Maximum 160 MHz, VDW = 152 for all core modules, but
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* CM926EJ-S, CM1026EJ-S and CM1136JF-S can actually
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* go to 200 MHz (max VDW = 192).
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*/
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.vd_max = 192,
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/* r is hardcoded to 22 and this is the actual divisor, +2 */
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.rd_min = 24,
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.rd_max = 24,
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.s2div = icst525_s2div,
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.idx2s = icst525_idx2s,
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};
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static const struct icst_params icst525_ap_sys_params = {
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.vco_max = ICST525_VCO_MAX_5V,
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.vco_min = ICST525_VCO_MIN,
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/* Minimum 3 MHz, VDW = 4 */
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.vd_min = 3,
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/* Maximum 50 MHz, VDW = 192 */
|
|
.vd_max = 50,
|
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/* r is hardcoded to 46 and this is the actual divisor, +2 */
|
|
.rd_min = 48,
|
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.rd_max = 48,
|
|
.s2div = icst525_s2div,
|
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.idx2s = icst525_idx2s,
|
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};
|
|
|
|
static const struct icst_params icst525_ap_pci_params = {
|
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.vco_max = ICST525_VCO_MAX_5V,
|
|
.vco_min = ICST525_VCO_MIN,
|
|
/* Minimum 25 MHz */
|
|
.vd_min = 25,
|
|
/* Maximum 33 MHz */
|
|
.vd_max = 33,
|
|
/* r is hardcoded to 14 or 22 and this is the actual divisors +2 */
|
|
.rd_min = 16,
|
|
.rd_max = 24,
|
|
.s2div = icst525_s2div,
|
|
.idx2s = icst525_idx2s,
|
|
};
|
|
|
|
static void __init of_syscon_icst_setup(struct device_node *np)
|
|
{
|
|
struct device_node *parent;
|
|
struct regmap *map;
|
|
struct clk_icst_desc icst_desc;
|
|
const char *name = np->name;
|
|
const char *parent_name;
|
|
struct clk *regclk;
|
|
enum icst_control_type ctype;
|
|
|
|
/* We do not release this reference, we are using it perpetually */
|
|
parent = of_get_parent(np);
|
|
if (!parent) {
|
|
pr_err("no parent node for syscon ICST clock\n");
|
|
return;
|
|
}
|
|
map = syscon_node_to_regmap(parent);
|
|
if (IS_ERR(map)) {
|
|
pr_err("no regmap for syscon ICST clock parent\n");
|
|
return;
|
|
}
|
|
|
|
if (of_property_read_u32(np, "vco-offset", &icst_desc.vco_offset)) {
|
|
pr_err("no VCO register offset for ICST clock\n");
|
|
return;
|
|
}
|
|
if (of_property_read_u32(np, "lock-offset", &icst_desc.lock_offset)) {
|
|
pr_err("no lock register offset for ICST clock\n");
|
|
return;
|
|
}
|
|
|
|
if (of_device_is_compatible(np, "arm,syscon-icst525")) {
|
|
icst_desc.params = &icst525_params;
|
|
ctype = ICST_VERSATILE;
|
|
} else if (of_device_is_compatible(np, "arm,syscon-icst307")) {
|
|
icst_desc.params = &icst307_params;
|
|
ctype = ICST_VERSATILE;
|
|
} else if (of_device_is_compatible(np, "arm,syscon-icst525-integratorap-cm")) {
|
|
icst_desc.params = &icst525_apcp_cm_params;
|
|
ctype = ICST_INTEGRATOR_AP_CM;
|
|
} else if (of_device_is_compatible(np, "arm,syscon-icst525-integratorap-sys")) {
|
|
icst_desc.params = &icst525_ap_sys_params;
|
|
ctype = ICST_INTEGRATOR_AP_SYS;
|
|
} else if (of_device_is_compatible(np, "arm,syscon-icst525-integratorap-pci")) {
|
|
icst_desc.params = &icst525_ap_pci_params;
|
|
ctype = ICST_INTEGRATOR_AP_PCI;
|
|
} else if (of_device_is_compatible(np, "arm,syscon-icst525-integratorcp-cm-core")) {
|
|
icst_desc.params = &icst525_apcp_cm_params;
|
|
ctype = ICST_INTEGRATOR_CP_CM_CORE;
|
|
} else if (of_device_is_compatible(np, "arm,syscon-icst525-integratorcp-cm-mem")) {
|
|
icst_desc.params = &icst525_apcp_cm_params;
|
|
ctype = ICST_INTEGRATOR_CP_CM_MEM;
|
|
} else {
|
|
pr_err("unknown ICST clock %s\n", name);
|
|
return;
|
|
}
|
|
|
|
/* Parent clock name is not the same as node parent */
|
|
parent_name = of_clk_get_parent_name(np, 0);
|
|
|
|
regclk = icst_clk_setup(NULL, &icst_desc, name, parent_name, map, ctype);
|
|
if (IS_ERR(regclk)) {
|
|
pr_err("error setting up syscon ICST clock %s\n", name);
|
|
return;
|
|
}
|
|
of_clk_add_provider(np, of_clk_src_simple_get, regclk);
|
|
pr_debug("registered syscon ICST clock %s\n", name);
|
|
}
|
|
|
|
CLK_OF_DECLARE(arm_syscon_icst525_clk,
|
|
"arm,syscon-icst525", of_syscon_icst_setup);
|
|
CLK_OF_DECLARE(arm_syscon_icst307_clk,
|
|
"arm,syscon-icst307", of_syscon_icst_setup);
|
|
CLK_OF_DECLARE(arm_syscon_integratorap_cm_clk,
|
|
"arm,syscon-icst525-integratorap-cm", of_syscon_icst_setup);
|
|
CLK_OF_DECLARE(arm_syscon_integratorap_sys_clk,
|
|
"arm,syscon-icst525-integratorap-sys", of_syscon_icst_setup);
|
|
CLK_OF_DECLARE(arm_syscon_integratorap_pci_clk,
|
|
"arm,syscon-icst525-integratorap-pci", of_syscon_icst_setup);
|
|
CLK_OF_DECLARE(arm_syscon_integratorcp_cm_core_clk,
|
|
"arm,syscon-icst525-integratorcp-cm-core", of_syscon_icst_setup);
|
|
CLK_OF_DECLARE(arm_syscon_integratorcp_cm_mem_clk,
|
|
"arm,syscon-icst525-integratorcp-cm-mem", of_syscon_icst_setup);
|
|
#endif
|