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![Shaokun Zhang](/assets/img/avatar_default.png)
MT bit in MPIDR_EL1 is now supported in certain HiSilicon platforms, so the mapping between sccl_id/ccl_id and affinity level needs to be updated from the generic encoding we originally used. Cc: John Garry <john.garry@huawei.com> Cc: Will Deacon <will.deacon@arm.com> Cc: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Shaokun Zhang <zhangshaokun@hisilicon.com> [will: fixed comment] Signed-off-by: Will Deacon <will.deacon@arm.com>
448 lines
12 KiB
C
448 lines
12 KiB
C
/*
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* HiSilicon SoC Hardware event counters support
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*
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* Copyright (C) 2017 Hisilicon Limited
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* Author: Anurup M <anurup.m@huawei.com>
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* Shaokun Zhang <zhangshaokun@hisilicon.com>
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*
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* This code is based on the uncore PMUs like arm-cci and arm-ccn.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/bitmap.h>
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#include <linux/bitops.h>
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#include <linux/bug.h>
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#include <linux/err.h>
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#include <linux/errno.h>
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#include <linux/interrupt.h>
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#include <asm/local64.h>
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#include "hisi_uncore_pmu.h"
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#define HISI_GET_EVENTID(ev) (ev->hw.config_base & 0xff)
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#define HISI_MAX_PERIOD(nr) (BIT_ULL(nr) - 1)
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/*
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* PMU format attributes
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*/
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ssize_t hisi_format_sysfs_show(struct device *dev,
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struct device_attribute *attr, char *buf)
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{
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struct dev_ext_attribute *eattr;
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eattr = container_of(attr, struct dev_ext_attribute, attr);
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return sprintf(buf, "%s\n", (char *)eattr->var);
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}
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/*
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* PMU event attributes
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*/
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ssize_t hisi_event_sysfs_show(struct device *dev,
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struct device_attribute *attr, char *page)
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{
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struct dev_ext_attribute *eattr;
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eattr = container_of(attr, struct dev_ext_attribute, attr);
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return sprintf(page, "config=0x%lx\n", (unsigned long)eattr->var);
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}
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/*
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* sysfs cpumask attributes. For uncore PMU, we only have a single CPU to show
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*/
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ssize_t hisi_cpumask_sysfs_show(struct device *dev,
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struct device_attribute *attr, char *buf)
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{
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struct hisi_pmu *hisi_pmu = to_hisi_pmu(dev_get_drvdata(dev));
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return sprintf(buf, "%d\n", hisi_pmu->on_cpu);
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}
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static bool hisi_validate_event_group(struct perf_event *event)
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{
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struct perf_event *sibling, *leader = event->group_leader;
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struct hisi_pmu *hisi_pmu = to_hisi_pmu(event->pmu);
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/* Include count for the event */
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int counters = 1;
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if (!is_software_event(leader)) {
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/*
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* We must NOT create groups containing mixed PMUs, although
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* software events are acceptable
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*/
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if (leader->pmu != event->pmu)
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return false;
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/* Increment counter for the leader */
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if (leader != event)
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counters++;
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}
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for_each_sibling_event(sibling, event->group_leader) {
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if (is_software_event(sibling))
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continue;
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if (sibling->pmu != event->pmu)
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return false;
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/* Increment counter for each sibling */
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counters++;
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}
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/* The group can not count events more than the counters in the HW */
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return counters <= hisi_pmu->num_counters;
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}
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int hisi_uncore_pmu_counter_valid(struct hisi_pmu *hisi_pmu, int idx)
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{
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return idx >= 0 && idx < hisi_pmu->num_counters;
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}
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int hisi_uncore_pmu_get_event_idx(struct perf_event *event)
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{
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struct hisi_pmu *hisi_pmu = to_hisi_pmu(event->pmu);
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unsigned long *used_mask = hisi_pmu->pmu_events.used_mask;
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u32 num_counters = hisi_pmu->num_counters;
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int idx;
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idx = find_first_zero_bit(used_mask, num_counters);
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if (idx == num_counters)
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return -EAGAIN;
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set_bit(idx, used_mask);
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return idx;
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}
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static void hisi_uncore_pmu_clear_event_idx(struct hisi_pmu *hisi_pmu, int idx)
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{
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if (!hisi_uncore_pmu_counter_valid(hisi_pmu, idx)) {
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dev_err(hisi_pmu->dev, "Unsupported event index:%d!\n", idx);
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return;
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}
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clear_bit(idx, hisi_pmu->pmu_events.used_mask);
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}
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int hisi_uncore_pmu_event_init(struct perf_event *event)
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{
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struct hw_perf_event *hwc = &event->hw;
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struct hisi_pmu *hisi_pmu;
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if (event->attr.type != event->pmu->type)
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return -ENOENT;
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/*
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* We do not support sampling as the counters are all
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* shared by all CPU cores in a CPU die(SCCL). Also we
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* do not support attach to a task(per-process mode)
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*/
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if (is_sampling_event(event) || event->attach_state & PERF_ATTACH_TASK)
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return -EOPNOTSUPP;
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/* counters do not have these bits */
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if (event->attr.exclude_user ||
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event->attr.exclude_kernel ||
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event->attr.exclude_host ||
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event->attr.exclude_guest ||
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event->attr.exclude_hv ||
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event->attr.exclude_idle)
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return -EINVAL;
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/*
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* The uncore counters not specific to any CPU, so cannot
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* support per-task
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*/
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if (event->cpu < 0)
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return -EINVAL;
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/*
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* Validate if the events in group does not exceed the
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* available counters in hardware.
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*/
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if (!hisi_validate_event_group(event))
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return -EINVAL;
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hisi_pmu = to_hisi_pmu(event->pmu);
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if (event->attr.config > hisi_pmu->check_event)
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return -EINVAL;
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if (hisi_pmu->on_cpu == -1)
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return -EINVAL;
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/*
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* We don't assign an index until we actually place the event onto
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* hardware. Use -1 to signify that we haven't decided where to put it
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* yet.
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*/
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hwc->idx = -1;
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hwc->config_base = event->attr.config;
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/* Enforce to use the same CPU for all events in this PMU */
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event->cpu = hisi_pmu->on_cpu;
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return 0;
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}
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/*
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* Set the counter to count the event that we're interested in,
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* and enable interrupt and counter.
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*/
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static void hisi_uncore_pmu_enable_event(struct perf_event *event)
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{
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struct hisi_pmu *hisi_pmu = to_hisi_pmu(event->pmu);
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struct hw_perf_event *hwc = &event->hw;
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hisi_pmu->ops->write_evtype(hisi_pmu, hwc->idx,
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HISI_GET_EVENTID(event));
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hisi_pmu->ops->enable_counter_int(hisi_pmu, hwc);
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hisi_pmu->ops->enable_counter(hisi_pmu, hwc);
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}
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/*
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* Disable counter and interrupt.
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*/
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static void hisi_uncore_pmu_disable_event(struct perf_event *event)
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{
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struct hisi_pmu *hisi_pmu = to_hisi_pmu(event->pmu);
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struct hw_perf_event *hwc = &event->hw;
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hisi_pmu->ops->disable_counter(hisi_pmu, hwc);
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hisi_pmu->ops->disable_counter_int(hisi_pmu, hwc);
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}
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void hisi_uncore_pmu_set_event_period(struct perf_event *event)
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{
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struct hisi_pmu *hisi_pmu = to_hisi_pmu(event->pmu);
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struct hw_perf_event *hwc = &event->hw;
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/*
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* The HiSilicon PMU counters support 32 bits or 48 bits, depending on
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* the PMU. We reduce it to 2^(counter_bits - 1) to account for the
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* extreme interrupt latency. So we could hopefully handle the overflow
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* interrupt before another 2^(counter_bits - 1) events occur and the
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* counter overtakes its previous value.
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*/
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u64 val = BIT_ULL(hisi_pmu->counter_bits - 1);
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local64_set(&hwc->prev_count, val);
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/* Write start value to the hardware event counter */
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hisi_pmu->ops->write_counter(hisi_pmu, hwc, val);
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}
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void hisi_uncore_pmu_event_update(struct perf_event *event)
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{
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struct hisi_pmu *hisi_pmu = to_hisi_pmu(event->pmu);
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struct hw_perf_event *hwc = &event->hw;
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u64 delta, prev_raw_count, new_raw_count;
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do {
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/* Read the count from the counter register */
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new_raw_count = hisi_pmu->ops->read_counter(hisi_pmu, hwc);
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prev_raw_count = local64_read(&hwc->prev_count);
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} while (local64_cmpxchg(&hwc->prev_count, prev_raw_count,
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new_raw_count) != prev_raw_count);
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/*
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* compute the delta
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*/
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delta = (new_raw_count - prev_raw_count) &
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HISI_MAX_PERIOD(hisi_pmu->counter_bits);
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local64_add(delta, &event->count);
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}
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void hisi_uncore_pmu_start(struct perf_event *event, int flags)
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{
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struct hisi_pmu *hisi_pmu = to_hisi_pmu(event->pmu);
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struct hw_perf_event *hwc = &event->hw;
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if (WARN_ON_ONCE(!(hwc->state & PERF_HES_STOPPED)))
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return;
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WARN_ON_ONCE(!(hwc->state & PERF_HES_UPTODATE));
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hwc->state = 0;
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hisi_uncore_pmu_set_event_period(event);
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if (flags & PERF_EF_RELOAD) {
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u64 prev_raw_count = local64_read(&hwc->prev_count);
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hisi_pmu->ops->write_counter(hisi_pmu, hwc, prev_raw_count);
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}
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hisi_uncore_pmu_enable_event(event);
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perf_event_update_userpage(event);
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}
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void hisi_uncore_pmu_stop(struct perf_event *event, int flags)
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{
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struct hw_perf_event *hwc = &event->hw;
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hisi_uncore_pmu_disable_event(event);
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WARN_ON_ONCE(hwc->state & PERF_HES_STOPPED);
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hwc->state |= PERF_HES_STOPPED;
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if (hwc->state & PERF_HES_UPTODATE)
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return;
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/* Read hardware counter and update the perf counter statistics */
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hisi_uncore_pmu_event_update(event);
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hwc->state |= PERF_HES_UPTODATE;
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}
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int hisi_uncore_pmu_add(struct perf_event *event, int flags)
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{
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struct hisi_pmu *hisi_pmu = to_hisi_pmu(event->pmu);
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struct hw_perf_event *hwc = &event->hw;
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int idx;
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hwc->state = PERF_HES_STOPPED | PERF_HES_UPTODATE;
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/* Get an available counter index for counting */
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idx = hisi_pmu->ops->get_event_idx(event);
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if (idx < 0)
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return idx;
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event->hw.idx = idx;
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hisi_pmu->pmu_events.hw_events[idx] = event;
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if (flags & PERF_EF_START)
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hisi_uncore_pmu_start(event, PERF_EF_RELOAD);
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return 0;
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}
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void hisi_uncore_pmu_del(struct perf_event *event, int flags)
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{
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struct hisi_pmu *hisi_pmu = to_hisi_pmu(event->pmu);
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struct hw_perf_event *hwc = &event->hw;
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hisi_uncore_pmu_stop(event, PERF_EF_UPDATE);
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hisi_uncore_pmu_clear_event_idx(hisi_pmu, hwc->idx);
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perf_event_update_userpage(event);
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hisi_pmu->pmu_events.hw_events[hwc->idx] = NULL;
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}
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void hisi_uncore_pmu_read(struct perf_event *event)
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{
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/* Read hardware counter and update the perf counter statistics */
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hisi_uncore_pmu_event_update(event);
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}
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void hisi_uncore_pmu_enable(struct pmu *pmu)
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{
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struct hisi_pmu *hisi_pmu = to_hisi_pmu(pmu);
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int enabled = bitmap_weight(hisi_pmu->pmu_events.used_mask,
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hisi_pmu->num_counters);
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if (!enabled)
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return;
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hisi_pmu->ops->start_counters(hisi_pmu);
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}
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void hisi_uncore_pmu_disable(struct pmu *pmu)
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{
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struct hisi_pmu *hisi_pmu = to_hisi_pmu(pmu);
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hisi_pmu->ops->stop_counters(hisi_pmu);
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}
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/*
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* Read Super CPU cluster and CPU cluster ID from MPIDR_EL1.
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* If multi-threading is supported, CCL_ID is the low 3-bits in MPIDR[Aff2]
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* and SCCL_ID is the upper 5-bits of Aff2 field; if not, SCCL_ID
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* is in MPIDR[Aff2] and CCL_ID is in MPIDR[Aff1].
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*/
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static void hisi_read_sccl_and_ccl_id(int *sccl_id, int *ccl_id)
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{
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u64 mpidr = read_cpuid_mpidr();
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if (mpidr & MPIDR_MT_BITMASK) {
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int aff2 = MPIDR_AFFINITY_LEVEL(mpidr, 2);
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if (sccl_id)
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*sccl_id = aff2 >> 3;
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if (ccl_id)
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*ccl_id = aff2 & 0x7;
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} else {
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if (sccl_id)
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*sccl_id = MPIDR_AFFINITY_LEVEL(mpidr, 2);
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if (ccl_id)
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*ccl_id = MPIDR_AFFINITY_LEVEL(mpidr, 1);
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}
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}
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/*
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* Check whether the CPU is associated with this uncore PMU
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*/
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static bool hisi_pmu_cpu_is_associated_pmu(struct hisi_pmu *hisi_pmu)
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{
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int sccl_id, ccl_id;
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if (hisi_pmu->ccl_id == -1) {
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/* If CCL_ID is -1, the PMU only shares the same SCCL */
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hisi_read_sccl_and_ccl_id(&sccl_id, NULL);
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return sccl_id == hisi_pmu->sccl_id;
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}
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hisi_read_sccl_and_ccl_id(&sccl_id, &ccl_id);
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return sccl_id == hisi_pmu->sccl_id && ccl_id == hisi_pmu->ccl_id;
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}
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int hisi_uncore_pmu_online_cpu(unsigned int cpu, struct hlist_node *node)
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{
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struct hisi_pmu *hisi_pmu = hlist_entry_safe(node, struct hisi_pmu,
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node);
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if (!hisi_pmu_cpu_is_associated_pmu(hisi_pmu))
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return 0;
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cpumask_set_cpu(cpu, &hisi_pmu->associated_cpus);
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/* If another CPU is already managing this PMU, simply return. */
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if (hisi_pmu->on_cpu != -1)
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return 0;
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/* Use this CPU in cpumask for event counting */
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hisi_pmu->on_cpu = cpu;
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/* Overflow interrupt also should use the same CPU */
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WARN_ON(irq_set_affinity(hisi_pmu->irq, cpumask_of(cpu)));
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return 0;
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}
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int hisi_uncore_pmu_offline_cpu(unsigned int cpu, struct hlist_node *node)
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{
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struct hisi_pmu *hisi_pmu = hlist_entry_safe(node, struct hisi_pmu,
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node);
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cpumask_t pmu_online_cpus;
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unsigned int target;
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if (!cpumask_test_and_clear_cpu(cpu, &hisi_pmu->associated_cpus))
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return 0;
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/* Nothing to do if this CPU doesn't own the PMU */
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if (hisi_pmu->on_cpu != cpu)
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return 0;
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/* Give up ownership of the PMU */
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hisi_pmu->on_cpu = -1;
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/* Choose a new CPU to migrate ownership of the PMU to */
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cpumask_and(&pmu_online_cpus, &hisi_pmu->associated_cpus,
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cpu_online_mask);
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target = cpumask_any_but(&pmu_online_cpus, cpu);
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if (target >= nr_cpu_ids)
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return 0;
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perf_pmu_migrate_context(&hisi_pmu->pmu, cpu, target);
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/* Use this CPU for event counting */
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hisi_pmu->on_cpu = target;
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WARN_ON(irq_set_affinity(hisi_pmu->irq, cpumask_of(target)));
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return 0;
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}
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