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![Kees Cook](/assets/img/avatar_default.png)
In preparation for unconditionally passing the struct timer_list pointer to all timer callbacks, switch to using the new timer_setup() and from_timer() to pass the timer pointer explicitly. This requires adding a pointer to hold the timer's target task, as there isn't a link back from slow_task. Cc: John Garry <john.garry@huawei.com> Cc: "James E.J. Bottomley" <jejb@linux.vnet.ibm.com> Cc: "Martin K. Petersen" <martin.petersen@oracle.com> Cc: Jack Wang <jinpu.wang@profitbricks.com> Cc: lindar_liu@usish.com Cc: Jens Axboe <axboe@fb.com> Cc: Hannes Reinecke <hare@suse.com> Cc: Johannes Thumshirn <jthumshirn@suse.de> Cc: Benjamin Block <bblock@linux.vnet.ibm.com> Cc: Baoyou Xie <baoyou.xie@linaro.org> Cc: Wei Yongjun <weiyongjun1@huawei.com> Cc: linux-scsi@vger.kernel.org Signed-off-by: Kees Cook <keescook@chromium.org> Reviewed-by: Martin K. Petersen <martin.petersen@oracle.com> Acked-by: John Garry <john.garry@huawei.com> # for hisi_sas part Tested-by: John Garry <john.garry@huawei.com> # basic sanity test for hisi_sas Reviewed-by: Jack Wang <jinpu.wang@profitbricks.com>
832 lines
21 KiB
C
832 lines
21 KiB
C
/*
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* Marvell 88SE64xx/88SE94xx pci init
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*
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* Copyright 2007 Red Hat, Inc.
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* Copyright 2008 Marvell. <kewei@marvell.com>
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* Copyright 2009-2011 Marvell. <yuxiangl@marvell.com>
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*
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* This file is licensed under GPLv2.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; version 2 of the
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* License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
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* USA
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*/
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#include "mv_sas.h"
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int interrupt_coalescing = 0x80;
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static struct scsi_transport_template *mvs_stt;
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static const struct mvs_chip_info mvs_chips[] = {
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[chip_6320] = { 1, 2, 0x400, 17, 16, 6, 9, &mvs_64xx_dispatch, },
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[chip_6440] = { 1, 4, 0x400, 17, 16, 6, 9, &mvs_64xx_dispatch, },
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[chip_6485] = { 1, 8, 0x800, 33, 32, 6, 10, &mvs_64xx_dispatch, },
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[chip_9180] = { 2, 4, 0x800, 17, 64, 8, 9, &mvs_94xx_dispatch, },
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[chip_9480] = { 2, 4, 0x800, 17, 64, 8, 9, &mvs_94xx_dispatch, },
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[chip_9445] = { 1, 4, 0x800, 17, 64, 8, 11, &mvs_94xx_dispatch, },
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[chip_9485] = { 2, 4, 0x800, 17, 64, 8, 11, &mvs_94xx_dispatch, },
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[chip_1300] = { 1, 4, 0x400, 17, 16, 6, 9, &mvs_64xx_dispatch, },
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[chip_1320] = { 2, 4, 0x800, 17, 64, 8, 9, &mvs_94xx_dispatch, },
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};
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struct device_attribute *mvst_host_attrs[];
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#define SOC_SAS_NUM 2
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static struct scsi_host_template mvs_sht = {
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.module = THIS_MODULE,
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.name = DRV_NAME,
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.queuecommand = sas_queuecommand,
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.target_alloc = sas_target_alloc,
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.slave_configure = sas_slave_configure,
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.scan_finished = mvs_scan_finished,
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.scan_start = mvs_scan_start,
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.change_queue_depth = sas_change_queue_depth,
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.bios_param = sas_bios_param,
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.can_queue = 1,
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.this_id = -1,
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.sg_tablesize = SG_ALL,
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.max_sectors = SCSI_DEFAULT_MAX_SECTORS,
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.use_clustering = ENABLE_CLUSTERING,
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.eh_device_reset_handler = sas_eh_device_reset_handler,
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.eh_target_reset_handler = sas_eh_target_reset_handler,
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.target_destroy = sas_target_destroy,
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.ioctl = sas_ioctl,
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.shost_attrs = mvst_host_attrs,
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.track_queue_depth = 1,
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};
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static struct sas_domain_function_template mvs_transport_ops = {
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.lldd_dev_found = mvs_dev_found,
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.lldd_dev_gone = mvs_dev_gone,
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.lldd_execute_task = mvs_queue_command,
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.lldd_control_phy = mvs_phy_control,
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.lldd_abort_task = mvs_abort_task,
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.lldd_abort_task_set = mvs_abort_task_set,
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.lldd_clear_aca = mvs_clear_aca,
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.lldd_clear_task_set = mvs_clear_task_set,
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.lldd_I_T_nexus_reset = mvs_I_T_nexus_reset,
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.lldd_lu_reset = mvs_lu_reset,
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.lldd_query_task = mvs_query_task,
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.lldd_port_formed = mvs_port_formed,
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.lldd_port_deformed = mvs_port_deformed,
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.lldd_write_gpio = mvs_gpio_write,
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};
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static void mvs_phy_init(struct mvs_info *mvi, int phy_id)
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{
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struct mvs_phy *phy = &mvi->phy[phy_id];
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struct asd_sas_phy *sas_phy = &phy->sas_phy;
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phy->mvi = mvi;
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phy->port = NULL;
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timer_setup(&phy->timer, NULL, 0);
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sas_phy->enabled = (phy_id < mvi->chip->n_phy) ? 1 : 0;
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sas_phy->class = SAS;
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sas_phy->iproto = SAS_PROTOCOL_ALL;
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sas_phy->tproto = 0;
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sas_phy->type = PHY_TYPE_PHYSICAL;
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sas_phy->role = PHY_ROLE_INITIATOR;
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sas_phy->oob_mode = OOB_NOT_CONNECTED;
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sas_phy->linkrate = SAS_LINK_RATE_UNKNOWN;
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sas_phy->id = phy_id;
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sas_phy->sas_addr = &mvi->sas_addr[0];
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sas_phy->frame_rcvd = &phy->frame_rcvd[0];
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sas_phy->ha = (struct sas_ha_struct *)mvi->shost->hostdata;
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sas_phy->lldd_phy = phy;
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}
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static void mvs_free(struct mvs_info *mvi)
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{
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struct mvs_wq *mwq;
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int slot_nr;
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if (!mvi)
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return;
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if (mvi->flags & MVF_FLAG_SOC)
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slot_nr = MVS_SOC_SLOTS;
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else
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slot_nr = MVS_CHIP_SLOT_SZ;
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dma_pool_destroy(mvi->dma_pool);
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if (mvi->tx)
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dma_free_coherent(mvi->dev,
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sizeof(*mvi->tx) * MVS_CHIP_SLOT_SZ,
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mvi->tx, mvi->tx_dma);
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if (mvi->rx_fis)
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dma_free_coherent(mvi->dev, MVS_RX_FISL_SZ,
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mvi->rx_fis, mvi->rx_fis_dma);
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if (mvi->rx)
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dma_free_coherent(mvi->dev,
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sizeof(*mvi->rx) * (MVS_RX_RING_SZ + 1),
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mvi->rx, mvi->rx_dma);
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if (mvi->slot)
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dma_free_coherent(mvi->dev,
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sizeof(*mvi->slot) * slot_nr,
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mvi->slot, mvi->slot_dma);
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if (mvi->bulk_buffer)
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dma_free_coherent(mvi->dev, TRASH_BUCKET_SIZE,
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mvi->bulk_buffer, mvi->bulk_buffer_dma);
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if (mvi->bulk_buffer1)
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dma_free_coherent(mvi->dev, TRASH_BUCKET_SIZE,
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mvi->bulk_buffer1, mvi->bulk_buffer_dma1);
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MVS_CHIP_DISP->chip_iounmap(mvi);
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if (mvi->shost)
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scsi_host_put(mvi->shost);
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list_for_each_entry(mwq, &mvi->wq_list, entry)
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cancel_delayed_work(&mwq->work_q);
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kfree(mvi->tags);
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kfree(mvi);
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}
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#ifdef CONFIG_SCSI_MVSAS_TASKLET
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static void mvs_tasklet(unsigned long opaque)
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{
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u32 stat;
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u16 core_nr, i = 0;
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struct mvs_info *mvi;
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struct sas_ha_struct *sha = (struct sas_ha_struct *)opaque;
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core_nr = ((struct mvs_prv_info *)sha->lldd_ha)->n_host;
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mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[0];
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if (unlikely(!mvi))
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BUG_ON(1);
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stat = MVS_CHIP_DISP->isr_status(mvi, mvi->pdev->irq);
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if (!stat)
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goto out;
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for (i = 0; i < core_nr; i++) {
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mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[i];
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MVS_CHIP_DISP->isr(mvi, mvi->pdev->irq, stat);
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}
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out:
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MVS_CHIP_DISP->interrupt_enable(mvi);
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}
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#endif
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static irqreturn_t mvs_interrupt(int irq, void *opaque)
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{
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u32 core_nr;
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u32 stat;
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struct mvs_info *mvi;
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struct sas_ha_struct *sha = opaque;
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#ifndef CONFIG_SCSI_MVSAS_TASKLET
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u32 i;
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#endif
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core_nr = ((struct mvs_prv_info *)sha->lldd_ha)->n_host;
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mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[0];
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if (unlikely(!mvi))
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return IRQ_NONE;
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#ifdef CONFIG_SCSI_MVSAS_TASKLET
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MVS_CHIP_DISP->interrupt_disable(mvi);
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#endif
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stat = MVS_CHIP_DISP->isr_status(mvi, irq);
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if (!stat) {
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#ifdef CONFIG_SCSI_MVSAS_TASKLET
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MVS_CHIP_DISP->interrupt_enable(mvi);
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#endif
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return IRQ_NONE;
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}
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#ifdef CONFIG_SCSI_MVSAS_TASKLET
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tasklet_schedule(&((struct mvs_prv_info *)sha->lldd_ha)->mv_tasklet);
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#else
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for (i = 0; i < core_nr; i++) {
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mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[i];
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MVS_CHIP_DISP->isr(mvi, irq, stat);
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}
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#endif
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return IRQ_HANDLED;
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}
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static int mvs_alloc(struct mvs_info *mvi, struct Scsi_Host *shost)
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{
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int i = 0, slot_nr;
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char pool_name[32];
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if (mvi->flags & MVF_FLAG_SOC)
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slot_nr = MVS_SOC_SLOTS;
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else
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slot_nr = MVS_CHIP_SLOT_SZ;
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spin_lock_init(&mvi->lock);
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for (i = 0; i < mvi->chip->n_phy; i++) {
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mvs_phy_init(mvi, i);
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mvi->port[i].wide_port_phymap = 0;
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mvi->port[i].port_attached = 0;
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INIT_LIST_HEAD(&mvi->port[i].list);
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}
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for (i = 0; i < MVS_MAX_DEVICES; i++) {
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mvi->devices[i].taskfileset = MVS_ID_NOT_MAPPED;
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mvi->devices[i].dev_type = SAS_PHY_UNUSED;
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mvi->devices[i].device_id = i;
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mvi->devices[i].dev_status = MVS_DEV_NORMAL;
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}
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/*
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* alloc and init our DMA areas
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*/
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mvi->tx = dma_alloc_coherent(mvi->dev,
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sizeof(*mvi->tx) * MVS_CHIP_SLOT_SZ,
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&mvi->tx_dma, GFP_KERNEL);
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if (!mvi->tx)
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goto err_out;
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memset(mvi->tx, 0, sizeof(*mvi->tx) * MVS_CHIP_SLOT_SZ);
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mvi->rx_fis = dma_alloc_coherent(mvi->dev, MVS_RX_FISL_SZ,
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&mvi->rx_fis_dma, GFP_KERNEL);
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if (!mvi->rx_fis)
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goto err_out;
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memset(mvi->rx_fis, 0, MVS_RX_FISL_SZ);
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mvi->rx = dma_alloc_coherent(mvi->dev,
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sizeof(*mvi->rx) * (MVS_RX_RING_SZ + 1),
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&mvi->rx_dma, GFP_KERNEL);
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if (!mvi->rx)
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goto err_out;
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memset(mvi->rx, 0, sizeof(*mvi->rx) * (MVS_RX_RING_SZ + 1));
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mvi->rx[0] = cpu_to_le32(0xfff);
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mvi->rx_cons = 0xfff;
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mvi->slot = dma_alloc_coherent(mvi->dev,
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sizeof(*mvi->slot) * slot_nr,
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&mvi->slot_dma, GFP_KERNEL);
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if (!mvi->slot)
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goto err_out;
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memset(mvi->slot, 0, sizeof(*mvi->slot) * slot_nr);
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mvi->bulk_buffer = dma_alloc_coherent(mvi->dev,
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TRASH_BUCKET_SIZE,
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&mvi->bulk_buffer_dma, GFP_KERNEL);
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if (!mvi->bulk_buffer)
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goto err_out;
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mvi->bulk_buffer1 = dma_alloc_coherent(mvi->dev,
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TRASH_BUCKET_SIZE,
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&mvi->bulk_buffer_dma1, GFP_KERNEL);
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if (!mvi->bulk_buffer1)
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goto err_out;
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sprintf(pool_name, "%s%d", "mvs_dma_pool", mvi->id);
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mvi->dma_pool = dma_pool_create(pool_name, &mvi->pdev->dev,
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MVS_SLOT_BUF_SZ, 16, 0);
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if (!mvi->dma_pool) {
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printk(KERN_DEBUG "failed to create dma pool %s.\n", pool_name);
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goto err_out;
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}
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mvi->tags_num = slot_nr;
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/* Initialize tags */
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mvs_tag_init(mvi);
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return 0;
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err_out:
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return 1;
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}
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int mvs_ioremap(struct mvs_info *mvi, int bar, int bar_ex)
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{
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unsigned long res_start, res_len, res_flag, res_flag_ex = 0;
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struct pci_dev *pdev = mvi->pdev;
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if (bar_ex != -1) {
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/*
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* ioremap main and peripheral registers
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*/
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res_start = pci_resource_start(pdev, bar_ex);
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res_len = pci_resource_len(pdev, bar_ex);
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if (!res_start || !res_len)
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goto err_out;
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res_flag_ex = pci_resource_flags(pdev, bar_ex);
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if (res_flag_ex & IORESOURCE_MEM)
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mvi->regs_ex = ioremap(res_start, res_len);
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else
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mvi->regs_ex = (void *)res_start;
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if (!mvi->regs_ex)
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goto err_out;
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}
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res_start = pci_resource_start(pdev, bar);
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res_len = pci_resource_len(pdev, bar);
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if (!res_start || !res_len) {
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iounmap(mvi->regs_ex);
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mvi->regs_ex = NULL;
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goto err_out;
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}
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res_flag = pci_resource_flags(pdev, bar);
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mvi->regs = ioremap(res_start, res_len);
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if (!mvi->regs) {
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if (mvi->regs_ex && (res_flag_ex & IORESOURCE_MEM))
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iounmap(mvi->regs_ex);
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mvi->regs_ex = NULL;
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goto err_out;
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}
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return 0;
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err_out:
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return -1;
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}
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void mvs_iounmap(void __iomem *regs)
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{
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iounmap(regs);
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}
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static struct mvs_info *mvs_pci_alloc(struct pci_dev *pdev,
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const struct pci_device_id *ent,
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struct Scsi_Host *shost, unsigned int id)
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{
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struct mvs_info *mvi = NULL;
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struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
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mvi = kzalloc(sizeof(*mvi) +
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(1L << mvs_chips[ent->driver_data].slot_width) *
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sizeof(struct mvs_slot_info), GFP_KERNEL);
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if (!mvi)
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return NULL;
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mvi->pdev = pdev;
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mvi->dev = &pdev->dev;
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mvi->chip_id = ent->driver_data;
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mvi->chip = &mvs_chips[mvi->chip_id];
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INIT_LIST_HEAD(&mvi->wq_list);
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((struct mvs_prv_info *)sha->lldd_ha)->mvi[id] = mvi;
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((struct mvs_prv_info *)sha->lldd_ha)->n_phy = mvi->chip->n_phy;
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mvi->id = id;
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mvi->sas = sha;
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mvi->shost = shost;
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mvi->tags = kzalloc(MVS_CHIP_SLOT_SZ>>3, GFP_KERNEL);
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if (!mvi->tags)
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goto err_out;
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if (MVS_CHIP_DISP->chip_ioremap(mvi))
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goto err_out;
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if (!mvs_alloc(mvi, shost))
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return mvi;
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err_out:
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mvs_free(mvi);
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return NULL;
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}
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static int pci_go_64(struct pci_dev *pdev)
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{
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int rc;
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if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
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rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
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if (rc) {
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rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
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if (rc) {
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dev_printk(KERN_ERR, &pdev->dev,
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"64-bit DMA enable failed\n");
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return rc;
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}
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}
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} else {
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rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
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if (rc) {
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dev_printk(KERN_ERR, &pdev->dev,
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"32-bit DMA enable failed\n");
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return rc;
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}
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rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
|
|
if (rc) {
|
|
dev_printk(KERN_ERR, &pdev->dev,
|
|
"32-bit consistent DMA enable failed\n");
|
|
return rc;
|
|
}
|
|
}
|
|
|
|
return rc;
|
|
}
|
|
|
|
static int mvs_prep_sas_ha_init(struct Scsi_Host *shost,
|
|
const struct mvs_chip_info *chip_info)
|
|
{
|
|
int phy_nr, port_nr; unsigned short core_nr;
|
|
struct asd_sas_phy **arr_phy;
|
|
struct asd_sas_port **arr_port;
|
|
struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
|
|
|
|
core_nr = chip_info->n_host;
|
|
phy_nr = core_nr * chip_info->n_phy;
|
|
port_nr = phy_nr;
|
|
|
|
memset(sha, 0x00, sizeof(struct sas_ha_struct));
|
|
arr_phy = kcalloc(phy_nr, sizeof(void *), GFP_KERNEL);
|
|
arr_port = kcalloc(port_nr, sizeof(void *), GFP_KERNEL);
|
|
if (!arr_phy || !arr_port)
|
|
goto exit_free;
|
|
|
|
sha->sas_phy = arr_phy;
|
|
sha->sas_port = arr_port;
|
|
sha->core.shost = shost;
|
|
|
|
sha->lldd_ha = kzalloc(sizeof(struct mvs_prv_info), GFP_KERNEL);
|
|
if (!sha->lldd_ha)
|
|
goto exit_free;
|
|
|
|
((struct mvs_prv_info *)sha->lldd_ha)->n_host = core_nr;
|
|
|
|
shost->transportt = mvs_stt;
|
|
shost->max_id = MVS_MAX_DEVICES;
|
|
shost->max_lun = ~0;
|
|
shost->max_channel = 1;
|
|
shost->max_cmd_len = 16;
|
|
|
|
return 0;
|
|
exit_free:
|
|
kfree(arr_phy);
|
|
kfree(arr_port);
|
|
return -1;
|
|
|
|
}
|
|
|
|
static void mvs_post_sas_ha_init(struct Scsi_Host *shost,
|
|
const struct mvs_chip_info *chip_info)
|
|
{
|
|
int can_queue, i = 0, j = 0;
|
|
struct mvs_info *mvi = NULL;
|
|
struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
|
|
unsigned short nr_core = ((struct mvs_prv_info *)sha->lldd_ha)->n_host;
|
|
|
|
for (j = 0; j < nr_core; j++) {
|
|
mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[j];
|
|
for (i = 0; i < chip_info->n_phy; i++) {
|
|
sha->sas_phy[j * chip_info->n_phy + i] =
|
|
&mvi->phy[i].sas_phy;
|
|
sha->sas_port[j * chip_info->n_phy + i] =
|
|
&mvi->port[i].sas_port;
|
|
}
|
|
}
|
|
|
|
sha->sas_ha_name = DRV_NAME;
|
|
sha->dev = mvi->dev;
|
|
sha->lldd_module = THIS_MODULE;
|
|
sha->sas_addr = &mvi->sas_addr[0];
|
|
|
|
sha->num_phys = nr_core * chip_info->n_phy;
|
|
|
|
if (mvi->flags & MVF_FLAG_SOC)
|
|
can_queue = MVS_SOC_CAN_QUEUE;
|
|
else
|
|
can_queue = MVS_CHIP_SLOT_SZ;
|
|
|
|
shost->sg_tablesize = min_t(u16, SG_ALL, MVS_MAX_SG);
|
|
shost->can_queue = can_queue;
|
|
mvi->shost->cmd_per_lun = MVS_QUEUE_SIZE;
|
|
sha->core.shost = mvi->shost;
|
|
}
|
|
|
|
static void mvs_init_sas_add(struct mvs_info *mvi)
|
|
{
|
|
u8 i;
|
|
for (i = 0; i < mvi->chip->n_phy; i++) {
|
|
mvi->phy[i].dev_sas_addr = 0x5005043011ab0000ULL;
|
|
mvi->phy[i].dev_sas_addr =
|
|
cpu_to_be64((u64)(*(u64 *)&mvi->phy[i].dev_sas_addr));
|
|
}
|
|
|
|
memcpy(mvi->sas_addr, &mvi->phy[0].dev_sas_addr, SAS_ADDR_SIZE);
|
|
}
|
|
|
|
static int mvs_pci_init(struct pci_dev *pdev, const struct pci_device_id *ent)
|
|
{
|
|
unsigned int rc, nhost = 0;
|
|
struct mvs_info *mvi;
|
|
struct mvs_prv_info *mpi;
|
|
irq_handler_t irq_handler = mvs_interrupt;
|
|
struct Scsi_Host *shost = NULL;
|
|
const struct mvs_chip_info *chip;
|
|
|
|
dev_printk(KERN_INFO, &pdev->dev,
|
|
"mvsas: driver version %s\n", DRV_VERSION);
|
|
rc = pci_enable_device(pdev);
|
|
if (rc)
|
|
goto err_out_enable;
|
|
|
|
pci_set_master(pdev);
|
|
|
|
rc = pci_request_regions(pdev, DRV_NAME);
|
|
if (rc)
|
|
goto err_out_disable;
|
|
|
|
rc = pci_go_64(pdev);
|
|
if (rc)
|
|
goto err_out_regions;
|
|
|
|
shost = scsi_host_alloc(&mvs_sht, sizeof(void *));
|
|
if (!shost) {
|
|
rc = -ENOMEM;
|
|
goto err_out_regions;
|
|
}
|
|
|
|
chip = &mvs_chips[ent->driver_data];
|
|
SHOST_TO_SAS_HA(shost) =
|
|
kcalloc(1, sizeof(struct sas_ha_struct), GFP_KERNEL);
|
|
if (!SHOST_TO_SAS_HA(shost)) {
|
|
scsi_host_put(shost);
|
|
rc = -ENOMEM;
|
|
goto err_out_regions;
|
|
}
|
|
|
|
rc = mvs_prep_sas_ha_init(shost, chip);
|
|
if (rc) {
|
|
scsi_host_put(shost);
|
|
rc = -ENOMEM;
|
|
goto err_out_regions;
|
|
}
|
|
|
|
pci_set_drvdata(pdev, SHOST_TO_SAS_HA(shost));
|
|
|
|
do {
|
|
mvi = mvs_pci_alloc(pdev, ent, shost, nhost);
|
|
if (!mvi) {
|
|
rc = -ENOMEM;
|
|
goto err_out_regions;
|
|
}
|
|
|
|
memset(&mvi->hba_info_param, 0xFF,
|
|
sizeof(struct hba_info_page));
|
|
|
|
mvs_init_sas_add(mvi);
|
|
|
|
mvi->instance = nhost;
|
|
rc = MVS_CHIP_DISP->chip_init(mvi);
|
|
if (rc) {
|
|
mvs_free(mvi);
|
|
goto err_out_regions;
|
|
}
|
|
nhost++;
|
|
} while (nhost < chip->n_host);
|
|
mpi = (struct mvs_prv_info *)(SHOST_TO_SAS_HA(shost)->lldd_ha);
|
|
#ifdef CONFIG_SCSI_MVSAS_TASKLET
|
|
tasklet_init(&(mpi->mv_tasklet), mvs_tasklet,
|
|
(unsigned long)SHOST_TO_SAS_HA(shost));
|
|
#endif
|
|
|
|
mvs_post_sas_ha_init(shost, chip);
|
|
|
|
rc = scsi_add_host(shost, &pdev->dev);
|
|
if (rc)
|
|
goto err_out_shost;
|
|
|
|
rc = sas_register_ha(SHOST_TO_SAS_HA(shost));
|
|
if (rc)
|
|
goto err_out_shost;
|
|
rc = request_irq(pdev->irq, irq_handler, IRQF_SHARED,
|
|
DRV_NAME, SHOST_TO_SAS_HA(shost));
|
|
if (rc)
|
|
goto err_not_sas;
|
|
|
|
MVS_CHIP_DISP->interrupt_enable(mvi);
|
|
|
|
scsi_scan_host(mvi->shost);
|
|
|
|
return 0;
|
|
|
|
err_not_sas:
|
|
sas_unregister_ha(SHOST_TO_SAS_HA(shost));
|
|
err_out_shost:
|
|
scsi_remove_host(mvi->shost);
|
|
err_out_regions:
|
|
pci_release_regions(pdev);
|
|
err_out_disable:
|
|
pci_disable_device(pdev);
|
|
err_out_enable:
|
|
return rc;
|
|
}
|
|
|
|
static void mvs_pci_remove(struct pci_dev *pdev)
|
|
{
|
|
unsigned short core_nr, i = 0;
|
|
struct sas_ha_struct *sha = pci_get_drvdata(pdev);
|
|
struct mvs_info *mvi = NULL;
|
|
|
|
core_nr = ((struct mvs_prv_info *)sha->lldd_ha)->n_host;
|
|
mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[0];
|
|
|
|
#ifdef CONFIG_SCSI_MVSAS_TASKLET
|
|
tasklet_kill(&((struct mvs_prv_info *)sha->lldd_ha)->mv_tasklet);
|
|
#endif
|
|
|
|
sas_unregister_ha(sha);
|
|
sas_remove_host(mvi->shost);
|
|
|
|
MVS_CHIP_DISP->interrupt_disable(mvi);
|
|
free_irq(mvi->pdev->irq, sha);
|
|
for (i = 0; i < core_nr; i++) {
|
|
mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[i];
|
|
mvs_free(mvi);
|
|
}
|
|
kfree(sha->sas_phy);
|
|
kfree(sha->sas_port);
|
|
kfree(sha);
|
|
pci_release_regions(pdev);
|
|
pci_disable_device(pdev);
|
|
return;
|
|
}
|
|
|
|
static struct pci_device_id mvs_pci_table[] = {
|
|
{ PCI_VDEVICE(MARVELL, 0x6320), chip_6320 },
|
|
{ PCI_VDEVICE(MARVELL, 0x6340), chip_6440 },
|
|
{
|
|
.vendor = PCI_VENDOR_ID_MARVELL,
|
|
.device = 0x6440,
|
|
.subvendor = PCI_ANY_ID,
|
|
.subdevice = 0x6480,
|
|
.class = 0,
|
|
.class_mask = 0,
|
|
.driver_data = chip_6485,
|
|
},
|
|
{ PCI_VDEVICE(MARVELL, 0x6440), chip_6440 },
|
|
{ PCI_VDEVICE(MARVELL, 0x6485), chip_6485 },
|
|
{ PCI_VDEVICE(MARVELL, 0x9480), chip_9480 },
|
|
{ PCI_VDEVICE(MARVELL, 0x9180), chip_9180 },
|
|
{ PCI_VDEVICE(ARECA, PCI_DEVICE_ID_ARECA_1300), chip_1300 },
|
|
{ PCI_VDEVICE(ARECA, PCI_DEVICE_ID_ARECA_1320), chip_1320 },
|
|
{ PCI_VDEVICE(ADAPTEC2, 0x0450), chip_6440 },
|
|
{ PCI_VDEVICE(TTI, 0x2710), chip_9480 },
|
|
{ PCI_VDEVICE(TTI, 0x2720), chip_9480 },
|
|
{ PCI_VDEVICE(TTI, 0x2721), chip_9480 },
|
|
{ PCI_VDEVICE(TTI, 0x2722), chip_9480 },
|
|
{ PCI_VDEVICE(TTI, 0x2740), chip_9480 },
|
|
{ PCI_VDEVICE(TTI, 0x2744), chip_9480 },
|
|
{ PCI_VDEVICE(TTI, 0x2760), chip_9480 },
|
|
{
|
|
.vendor = PCI_VENDOR_ID_MARVELL_EXT,
|
|
.device = 0x9480,
|
|
.subvendor = PCI_ANY_ID,
|
|
.subdevice = 0x9480,
|
|
.class = 0,
|
|
.class_mask = 0,
|
|
.driver_data = chip_9480,
|
|
},
|
|
{
|
|
.vendor = PCI_VENDOR_ID_MARVELL_EXT,
|
|
.device = 0x9445,
|
|
.subvendor = PCI_ANY_ID,
|
|
.subdevice = 0x9480,
|
|
.class = 0,
|
|
.class_mask = 0,
|
|
.driver_data = chip_9445,
|
|
},
|
|
{ PCI_VDEVICE(MARVELL_EXT, 0x9485), chip_9485 }, /* Marvell 9480/9485 (any vendor/model) */
|
|
{ PCI_VDEVICE(OCZ, 0x1021), chip_9485}, /* OCZ RevoDrive3 */
|
|
{ PCI_VDEVICE(OCZ, 0x1022), chip_9485}, /* OCZ RevoDrive3/zDriveR4 (exact model unknown) */
|
|
{ PCI_VDEVICE(OCZ, 0x1040), chip_9485}, /* OCZ RevoDrive3/zDriveR4 (exact model unknown) */
|
|
{ PCI_VDEVICE(OCZ, 0x1041), chip_9485}, /* OCZ RevoDrive3/zDriveR4 (exact model unknown) */
|
|
{ PCI_VDEVICE(OCZ, 0x1042), chip_9485}, /* OCZ RevoDrive3/zDriveR4 (exact model unknown) */
|
|
{ PCI_VDEVICE(OCZ, 0x1043), chip_9485}, /* OCZ RevoDrive3/zDriveR4 (exact model unknown) */
|
|
{ PCI_VDEVICE(OCZ, 0x1044), chip_9485}, /* OCZ RevoDrive3/zDriveR4 (exact model unknown) */
|
|
{ PCI_VDEVICE(OCZ, 0x1080), chip_9485}, /* OCZ RevoDrive3/zDriveR4 (exact model unknown) */
|
|
{ PCI_VDEVICE(OCZ, 0x1083), chip_9485}, /* OCZ RevoDrive3/zDriveR4 (exact model unknown) */
|
|
{ PCI_VDEVICE(OCZ, 0x1084), chip_9485}, /* OCZ RevoDrive3/zDriveR4 (exact model unknown) */
|
|
|
|
{ } /* terminate list */
|
|
};
|
|
|
|
static struct pci_driver mvs_pci_driver = {
|
|
.name = DRV_NAME,
|
|
.id_table = mvs_pci_table,
|
|
.probe = mvs_pci_init,
|
|
.remove = mvs_pci_remove,
|
|
};
|
|
|
|
static ssize_t
|
|
mvs_show_driver_version(struct device *cdev,
|
|
struct device_attribute *attr, char *buffer)
|
|
{
|
|
return snprintf(buffer, PAGE_SIZE, "%s\n", DRV_VERSION);
|
|
}
|
|
|
|
static DEVICE_ATTR(driver_version,
|
|
S_IRUGO,
|
|
mvs_show_driver_version,
|
|
NULL);
|
|
|
|
static ssize_t
|
|
mvs_store_interrupt_coalescing(struct device *cdev,
|
|
struct device_attribute *attr,
|
|
const char *buffer, size_t size)
|
|
{
|
|
unsigned int val = 0;
|
|
struct mvs_info *mvi = NULL;
|
|
struct Scsi_Host *shost = class_to_shost(cdev);
|
|
struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
|
|
u8 i, core_nr;
|
|
if (buffer == NULL)
|
|
return size;
|
|
|
|
if (sscanf(buffer, "%u", &val) != 1)
|
|
return -EINVAL;
|
|
|
|
if (val >= 0x10000) {
|
|
mv_dprintk("interrupt coalescing timer %d us is"
|
|
"too long\n", val);
|
|
return strlen(buffer);
|
|
}
|
|
|
|
interrupt_coalescing = val;
|
|
|
|
core_nr = ((struct mvs_prv_info *)sha->lldd_ha)->n_host;
|
|
mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[0];
|
|
|
|
if (unlikely(!mvi))
|
|
return -EINVAL;
|
|
|
|
for (i = 0; i < core_nr; i++) {
|
|
mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[i];
|
|
if (MVS_CHIP_DISP->tune_interrupt)
|
|
MVS_CHIP_DISP->tune_interrupt(mvi,
|
|
interrupt_coalescing);
|
|
}
|
|
mv_dprintk("set interrupt coalescing time to %d us\n",
|
|
interrupt_coalescing);
|
|
return strlen(buffer);
|
|
}
|
|
|
|
static ssize_t mvs_show_interrupt_coalescing(struct device *cdev,
|
|
struct device_attribute *attr, char *buffer)
|
|
{
|
|
return snprintf(buffer, PAGE_SIZE, "%d\n", interrupt_coalescing);
|
|
}
|
|
|
|
static DEVICE_ATTR(interrupt_coalescing,
|
|
S_IRUGO|S_IWUSR,
|
|
mvs_show_interrupt_coalescing,
|
|
mvs_store_interrupt_coalescing);
|
|
|
|
/* task handler */
|
|
struct task_struct *mvs_th;
|
|
static int __init mvs_init(void)
|
|
{
|
|
int rc;
|
|
mvs_stt = sas_domain_attach_transport(&mvs_transport_ops);
|
|
if (!mvs_stt)
|
|
return -ENOMEM;
|
|
|
|
rc = pci_register_driver(&mvs_pci_driver);
|
|
if (rc)
|
|
goto err_out;
|
|
|
|
return 0;
|
|
|
|
err_out:
|
|
sas_release_transport(mvs_stt);
|
|
return rc;
|
|
}
|
|
|
|
static void __exit mvs_exit(void)
|
|
{
|
|
pci_unregister_driver(&mvs_pci_driver);
|
|
sas_release_transport(mvs_stt);
|
|
}
|
|
|
|
struct device_attribute *mvst_host_attrs[] = {
|
|
&dev_attr_driver_version,
|
|
&dev_attr_interrupt_coalescing,
|
|
NULL,
|
|
};
|
|
|
|
module_init(mvs_init);
|
|
module_exit(mvs_exit);
|
|
|
|
MODULE_AUTHOR("Jeff Garzik <jgarzik@pobox.com>");
|
|
MODULE_DESCRIPTION("Marvell 88SE6440 SAS/SATA controller driver");
|
|
MODULE_VERSION(DRV_VERSION);
|
|
MODULE_LICENSE("GPL");
|
|
#ifdef CONFIG_PCI
|
|
MODULE_DEVICE_TABLE(pci, mvs_pci_table);
|
|
#endif
|