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Baikal-T1 is supposed to be supplied with a high-frequency external oscillator. But in order to create signals suitable for each IP-block embedded into the SoC the oscillator output is primarily connected to a set of CCU PLLs. There are five of them to create clocks for the MIPS P5600 cores, an embedded DDR controller, SATA, Ethernet and PCIe domains. The last three domains though named by the biggest system interfaces in fact include nearly all of the rest SoC peripherals. Each of the PLLs is based on True Circuits TSMC CLN28HPM IP-core with an interface wrapper (so called safe PLL' clocks switcher) to simplify the PLL configuration procedure. This driver creates the of-based hardware clocks to use them then in the corresponding subsystems. In order to simplify the driver code we split the functionality up into the PLLs clocks operations and hardware clocks declaration/registration procedures. Even though the PLLs are based on the same IP-core, they may have some differences. In particular, some CCU PLLs support the output clock change without gating them (like CPU or PCIe PLLs), while the others don't, some CCU PLLs are critical and aren't supposed to be gated. In order to cover all of these cases the hardware clocks driver is designed with an info-descriptor pattern. So there are special static descriptors declared for each PLL, which is then used to create a hardware clock with proper operations. Additionally debugfs-files are provided for each PLL' field to make sure the implemented rate-PLLs-dividers calculation algorithm is correct. Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru> Cc: Alexey Malahov <Alexey.Malahov@baikalelectronics.ru> Cc: Arnd Bergmann <arnd@arndb.de> Cc: Rob Herring <robh+dt@kernel.org> Cc: linux-mips@vger.kernel.org Cc: devicetree@vger.kernel.org Link: https://lore.kernel.org/r/20200526222056.18072-4-Sergey.Semin@baikalelectronics.ru [sboyd@kernel.org: Silence sparse warning about initializing structs with NULL vs. integer] Signed-off-by: Stephen Boyd <sboyd@kernel.org>
64 lines
1.6 KiB
C
64 lines
1.6 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (C) 2020 BAIKAL ELECTRONICS, JSC
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*
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* Baikal-T1 CCU PLL interface driver
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*/
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#ifndef __CLK_BT1_CCU_PLL_H__
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#define __CLK_BT1_CCU_PLL_H__
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#include <linux/clk-provider.h>
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#include <linux/spinlock.h>
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#include <linux/regmap.h>
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#include <linux/bits.h>
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#include <linux/of.h>
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/*
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* struct ccu_pll_init_data - CCU PLL initialization data
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* @id: Clock private identifier.
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* @name: Clocks name.
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* @parent_name: Clocks parent name in a fw node.
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* @base: PLL registers base address with respect to the sys_regs base.
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* @sys_regs: Baikal-T1 System Controller registers map.
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* @np: Pointer to the node describing the CCU PLLs.
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* @flags: PLL clock flags.
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*/
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struct ccu_pll_init_data {
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unsigned int id;
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const char *name;
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const char *parent_name;
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unsigned int base;
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struct regmap *sys_regs;
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struct device_node *np;
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unsigned long flags;
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};
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/*
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* struct ccu_pll - CCU PLL descriptor
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* @hw: clk_hw of the PLL.
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* @id: Clock private identifier.
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* @reg_ctl: PLL control register base.
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* @reg_ctl1: PLL control1 register base.
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* @sys_regs: Baikal-T1 System Controller registers map.
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* @lock: PLL state change spin-lock.
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*/
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struct ccu_pll {
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struct clk_hw hw;
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unsigned int id;
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unsigned int reg_ctl;
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unsigned int reg_ctl1;
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struct regmap *sys_regs;
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spinlock_t lock;
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};
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#define to_ccu_pll(_hw) container_of(_hw, struct ccu_pll, hw)
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static inline struct clk_hw *ccu_pll_get_clk_hw(struct ccu_pll *pll)
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{
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return pll ? &pll->hw : NULL;
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}
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struct ccu_pll *ccu_pll_hw_register(const struct ccu_pll_init_data *init);
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void ccu_pll_hw_unregister(struct ccu_pll *pll);
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#endif /* __CLK_BT1_CCU_PLL_H__ */
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