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645b302673
PXA and StrongARM1100 traditionally map their I/O space 1:1 into virtual memory, using a per-bus io_offset that matches the base address of the ioremap mapping. In order for PXA to work in a multiplatform config, this needs to change so I/O space starts at PCI_IOBASE (0xfee00000). Since the pcmcia soc_common support is shared with StrongARM1100, both have to change at the same time. The affected machines are: - Anything with a PCMCIA slot now uses pci_remap_iospace, which is made available to PCMCIA configurations as well, rather than just PCI. The first PCMCIA slot now starts at port number 0x10000. - The Zeus and Viper platforms have PC/104-style ISA buses, which have a static mapping for both I/O and memory space at 0xf1000000, which can no longer work. It does not appear to have any in-tree users, so moving it to port number 0 makes them behave like a traditional PC. - SA1100 does support ISA slots in theory, but all machines that originally enabled this appear to have been removed from the tree ages ago, and the I/O space is never mapped anywhere. - The Nanoengine machine has support for PCI slots, but looks like this never included I/O space, the resources only define the location for memory and config space. With this, the definitions of __io() and IO_SPACE_LIMIT can be simplified, as the only remaining cases are the generic PCI_IOBASE and the custom inb()/outb() macros on RiscPC. S3C24xx still has a custom inb()/outb() in this here, but this is already removed in another branch. Signed-off-by: Arnd Bergmann <arnd@arndb.de>
125 lines
2.8 KiB
C
125 lines
2.8 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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#include <pcmcia/ss.h>
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struct module;
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struct cpufreq_freqs;
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struct soc_pcmcia_regulator {
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struct regulator *reg;
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bool on;
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};
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struct pcmcia_state {
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unsigned detect: 1,
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ready: 1,
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bvd1: 1,
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bvd2: 1,
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wrprot: 1,
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vs_3v: 1,
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vs_Xv: 1;
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};
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/*
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* This structure encapsulates per-socket state which we might need to
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* use when responding to a Card Services query of some kind.
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*/
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struct soc_pcmcia_socket {
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struct pcmcia_socket socket;
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/*
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* Info from low level handler
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*/
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unsigned int nr;
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struct clk *clk;
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/*
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* Core PCMCIA state
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*/
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const struct pcmcia_low_level *ops;
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unsigned int status;
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socket_state_t cs_state;
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unsigned short spd_io[MAX_IO_WIN];
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unsigned short spd_mem[MAX_WIN];
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unsigned short spd_attr[MAX_WIN];
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struct resource res_skt;
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struct resource res_io;
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struct resource res_io_io;
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struct resource res_mem;
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struct resource res_attr;
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struct {
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int gpio;
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struct gpio_desc *desc;
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unsigned int irq;
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const char *name;
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} stat[6];
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#define SOC_STAT_CD 0 /* Card detect */
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#define SOC_STAT_BVD1 1 /* BATDEAD / IOSTSCHG */
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#define SOC_STAT_BVD2 2 /* BATWARN / IOSPKR */
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#define SOC_STAT_RDY 3 /* Ready / Interrupt */
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#define SOC_STAT_VS1 4 /* Voltage sense 1 */
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#define SOC_STAT_VS2 5 /* Voltage sense 2 */
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struct gpio_desc *gpio_reset;
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struct gpio_desc *gpio_bus_enable;
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struct soc_pcmcia_regulator vcc;
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struct soc_pcmcia_regulator vpp;
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unsigned int irq_state;
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#ifdef CONFIG_CPU_FREQ
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struct notifier_block cpufreq_nb;
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#endif
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struct timer_list poll_timer;
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struct list_head node;
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void *driver_data;
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};
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struct pcmcia_low_level {
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struct module *owner;
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/* first socket in system */
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int first;
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/* nr of sockets */
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int nr;
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int (*hw_init)(struct soc_pcmcia_socket *);
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void (*hw_shutdown)(struct soc_pcmcia_socket *);
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void (*socket_state)(struct soc_pcmcia_socket *, struct pcmcia_state *);
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int (*configure_socket)(struct soc_pcmcia_socket *, const socket_state_t *);
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/*
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* Enable card status IRQs on (re-)initialisation. This can
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* be called at initialisation, power management event, or
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* pcmcia event.
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*/
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void (*socket_init)(struct soc_pcmcia_socket *);
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/*
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* Disable card status IRQs and PCMCIA bus on suspend.
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*/
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void (*socket_suspend)(struct soc_pcmcia_socket *);
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/*
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* Hardware specific timing routines.
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* If provided, the get_timing routine overrides the SOC default.
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*/
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unsigned int (*get_timing)(struct soc_pcmcia_socket *, unsigned int, unsigned int);
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int (*set_timing)(struct soc_pcmcia_socket *);
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int (*show_timing)(struct soc_pcmcia_socket *, char *);
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#ifdef CONFIG_CPU_FREQ
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/*
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* CPUFREQ support.
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*/
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int (*frequency_change)(struct soc_pcmcia_socket *, unsigned long, struct cpufreq_freqs *);
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#endif
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};
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