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4e486a6501
Support for the Exynos4212 SoC was originally dropped as there were
no boards using it. We will be adding a device that uses it, so add
back the relevant code.
This reverts commit 9e43eca3c8.
Signed-off-by: Artur Weber <aweber.kernel@gmail.com>
Link: https://lore.kernel.org/r/20230501195525.6268-4-aweber.kernel@gmail.com
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
261 lines
6.1 KiB
C
261 lines
6.1 KiB
C
// SPDX-License-Identifier: GPL-2.0
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//
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// Copyright (C) 2012 Samsung Electronics.
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// Kyungmin Park <kyungmin.park@samsung.com>
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// Tomasz Figa <t.figa@samsung.com>
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#include <linux/kernel.h>
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#include <linux/io.h>
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#include <linux/init.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <asm/cacheflush.h>
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#include <asm/cputype.h>
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#include <asm/firmware.h>
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#include <asm/hardware/cache-l2x0.h>
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#include <asm/suspend.h>
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#include "common.h"
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#include "smc.h"
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#define EXYNOS_BOOT_ADDR 0x8
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#define EXYNOS_BOOT_FLAG 0xc
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static void exynos_save_cp15(void)
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{
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/* Save Power control and Diagnostic registers */
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asm ("mrc p15, 0, %0, c15, c0, 0\n"
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"mrc p15, 0, %1, c15, c0, 1\n"
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: "=r" (cp15_save_power), "=r" (cp15_save_diag)
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: : "cc");
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}
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static int exynos_do_idle(unsigned long mode)
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{
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switch (mode) {
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case FW_DO_IDLE_AFTR:
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if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9)
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exynos_save_cp15();
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writel_relaxed(__pa_symbol(exynos_cpu_resume_ns),
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sysram_ns_base_addr + 0x24);
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writel_relaxed(EXYNOS_AFTR_MAGIC, sysram_ns_base_addr + 0x20);
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if (soc_is_exynos3250()) {
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flush_cache_all();
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exynos_smc(SMC_CMD_SAVE, OP_TYPE_CORE,
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SMC_POWERSTATE_IDLE, 0);
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exynos_smc(SMC_CMD_SHUTDOWN, OP_TYPE_CLUSTER,
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SMC_POWERSTATE_IDLE, 0);
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} else
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exynos_smc(SMC_CMD_CPU0AFTR, 0, 0, 0);
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break;
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case FW_DO_IDLE_SLEEP:
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exynos_smc(SMC_CMD_SLEEP, 0, 0, 0);
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}
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return 0;
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}
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static int exynos_cpu_boot(int cpu)
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{
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/*
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* Exynos3250 doesn't need to send smc command for secondary CPU boot
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* because Exynos3250 removes WFE in secure mode.
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*
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* On Exynos5 devices the call is ignored by trustzone firmware.
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*/
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if (!soc_is_exynos4210() && !soc_is_exynos4212() &&
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!soc_is_exynos4412())
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return 0;
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/*
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* The second parameter of SMC_CMD_CPU1BOOT command means CPU id.
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* But, Exynos4212 has only one secondary CPU so second parameter
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* isn't used for informing secure firmware about CPU id.
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*/
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if (soc_is_exynos4212())
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cpu = 0;
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exynos_smc(SMC_CMD_CPU1BOOT, cpu, 0, 0);
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return 0;
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}
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static int exynos_set_cpu_boot_addr(int cpu, unsigned long boot_addr)
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{
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void __iomem *boot_reg;
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if (!sysram_ns_base_addr)
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return -ENODEV;
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boot_reg = sysram_ns_base_addr + 0x1c;
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/*
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* Almost all Exynos-series of SoCs that run in secure mode don't need
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* additional offset for every CPU, with Exynos4412 being the only
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* exception.
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*/
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if (soc_is_exynos4412())
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boot_reg += 4 * cpu;
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writel_relaxed(boot_addr, boot_reg);
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return 0;
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}
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static int exynos_get_cpu_boot_addr(int cpu, unsigned long *boot_addr)
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{
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void __iomem *boot_reg;
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if (!sysram_ns_base_addr)
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return -ENODEV;
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boot_reg = sysram_ns_base_addr + 0x1c;
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if (soc_is_exynos4412())
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boot_reg += 4 * cpu;
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*boot_addr = readl_relaxed(boot_reg);
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return 0;
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}
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static int exynos_cpu_suspend(unsigned long arg)
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{
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flush_cache_all();
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outer_flush_all();
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exynos_smc(SMC_CMD_SLEEP, 0, 0, 0);
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pr_info("Failed to suspend the system\n");
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writel(0, sysram_ns_base_addr + EXYNOS_BOOT_FLAG);
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return 1;
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}
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static int exynos_suspend(void)
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{
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if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9)
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exynos_save_cp15();
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writel(EXYNOS_SLEEP_MAGIC, sysram_ns_base_addr + EXYNOS_BOOT_FLAG);
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writel(__pa_symbol(exynos_cpu_resume_ns),
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sysram_ns_base_addr + EXYNOS_BOOT_ADDR);
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return cpu_suspend(0, exynos_cpu_suspend);
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}
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static int exynos_resume(void)
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{
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writel(0, sysram_ns_base_addr + EXYNOS_BOOT_FLAG);
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return 0;
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}
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static const struct firmware_ops exynos_firmware_ops = {
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.do_idle = IS_ENABLED(CONFIG_EXYNOS_CPU_SUSPEND) ? exynos_do_idle : NULL,
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.set_cpu_boot_addr = exynos_set_cpu_boot_addr,
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.get_cpu_boot_addr = exynos_get_cpu_boot_addr,
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.cpu_boot = exynos_cpu_boot,
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.suspend = IS_ENABLED(CONFIG_PM_SLEEP) ? exynos_suspend : NULL,
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.resume = IS_ENABLED(CONFIG_EXYNOS_CPU_SUSPEND) ? exynos_resume : NULL,
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};
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static void exynos_l2_write_sec(unsigned long val, unsigned reg)
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{
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static int l2cache_enabled;
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switch (reg) {
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case L2X0_CTRL:
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if (val & L2X0_CTRL_EN) {
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/*
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* Before the cache can be enabled, due to firmware
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* design, SMC_CMD_L2X0INVALL must be called.
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*/
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if (!l2cache_enabled) {
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exynos_smc(SMC_CMD_L2X0INVALL, 0, 0, 0);
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l2cache_enabled = 1;
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}
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} else {
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l2cache_enabled = 0;
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}
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exynos_smc(SMC_CMD_L2X0CTRL, val, 0, 0);
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break;
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case L2X0_DEBUG_CTRL:
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exynos_smc(SMC_CMD_L2X0DEBUG, val, 0, 0);
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break;
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default:
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WARN_ONCE(1, "%s: ignoring write to reg 0x%x\n", __func__, reg);
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}
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}
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static void exynos_l2_configure(const struct l2x0_regs *regs)
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{
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exynos_smc(SMC_CMD_L2X0SETUP1, regs->tag_latency, regs->data_latency,
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regs->prefetch_ctrl);
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exynos_smc(SMC_CMD_L2X0SETUP2, regs->pwr_ctrl, regs->aux_ctrl, 0);
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}
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bool __init exynos_secure_firmware_available(void)
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{
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struct device_node *nd;
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const __be32 *addr;
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nd = of_find_compatible_node(NULL, NULL,
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"samsung,secure-firmware");
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if (!nd)
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return false;
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addr = of_get_address(nd, 0, NULL, NULL);
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of_node_put(nd);
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if (!addr) {
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pr_err("%s: No address specified.\n", __func__);
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return false;
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}
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return true;
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}
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void __init exynos_firmware_init(void)
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{
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if (!exynos_secure_firmware_available())
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return;
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pr_info("Running under secure firmware.\n");
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register_firmware_ops(&exynos_firmware_ops);
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/*
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* Exynos 4 SoCs (based on Cortex A9 and equipped with L2C-310),
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* running under secure firmware, require certain registers of L2
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* cache controller to be written in secure mode. Here .write_sec
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* callback is provided to perform necessary SMC calls.
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*/
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if (IS_ENABLED(CONFIG_CACHE_L2X0) &&
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read_cpuid_part() == ARM_CPU_PART_CORTEX_A9) {
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outer_cache.write_sec = exynos_l2_write_sec;
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outer_cache.configure = exynos_l2_configure;
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}
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}
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#define REG_CPU_STATE_ADDR (sysram_ns_base_addr + 0x28)
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#define BOOT_MODE_MASK 0x1f
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void exynos_set_boot_flag(unsigned int cpu, unsigned int mode)
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{
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unsigned int tmp;
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tmp = readl_relaxed(REG_CPU_STATE_ADDR + cpu * 4);
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if (mode & BOOT_MODE_MASK)
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tmp &= ~BOOT_MODE_MASK;
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tmp |= mode;
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writel_relaxed(tmp, REG_CPU_STATE_ADDR + cpu * 4);
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}
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void exynos_clear_boot_flag(unsigned int cpu, unsigned int mode)
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{
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unsigned int tmp;
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tmp = readl_relaxed(REG_CPU_STATE_ADDR + cpu * 4);
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tmp &= ~mode;
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writel_relaxed(tmp, REG_CPU_STATE_ADDR + cpu * 4);
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}
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