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58919326e7
Tegra234 supports sending/receiving 32-bit and 128-bit data over a shared mailbox. Based on the data size to be used, clients need to specify the type of shared mailbox in the device tree. Add a macro for 128-bit shared mailbox. Mailbox clients can use this macro as a flag in device tree to enable 128-bit data support for a shared mailbox. Signed-off-by: Kartik <kkartik@nvidia.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
41 lines
1.2 KiB
C
41 lines
1.2 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* This header provides constants for binding nvidia,tegra186-hsp.
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*/
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#ifndef _DT_BINDINGS_MAILBOX_TEGRA186_HSP_H
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#define _DT_BINDINGS_MAILBOX_TEGRA186_HSP_H
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/*
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* These define the type of mailbox that is to be used (doorbell, shared
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* mailbox, shared semaphore or arbitrated semaphore).
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*/
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#define TEGRA_HSP_MBOX_TYPE_DB 0x0
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#define TEGRA_HSP_MBOX_TYPE_SM 0x1
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#define TEGRA_HSP_MBOX_TYPE_SS 0x2
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#define TEGRA_HSP_MBOX_TYPE_AS 0x3
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/*
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* These define the types of shared mailbox supported based on data size.
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*/
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#define TEGRA_HSP_MBOX_TYPE_SM_128BIT (1 << 8)
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/*
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* These defines represent the bit associated with the given master ID in the
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* doorbell registers.
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*/
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#define TEGRA_HSP_DB_MASTER_CCPLEX 17
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#define TEGRA_HSP_DB_MASTER_BPMP 19
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/*
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* Shared mailboxes are unidirectional, so the direction needs to be specified
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* in the device tree.
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*/
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#define TEGRA_HSP_SM_MASK 0x00ffffff
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#define TEGRA_HSP_SM_FLAG_RX (0 << 31)
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#define TEGRA_HSP_SM_FLAG_TX (1 << 31)
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#define TEGRA_HSP_SM_RX(x) (TEGRA_HSP_SM_FLAG_RX | ((x) & TEGRA_HSP_SM_MASK))
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#define TEGRA_HSP_SM_TX(x) (TEGRA_HSP_SM_FLAG_TX | ((x) & TEGRA_HSP_SM_MASK))
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#endif
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