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0045e0d3f4
The current write wqe mechanism is to write to DDR first, and then notify the hardware through doorbell to read the data. Direct wqe is a mechanism to fill wqe directly into the hardware. In the case of light load, the wqe will be filled into pcie bar space of the hardware, this will reduce one memory access operation and therefore reduce the latency. SIMD instructions allows cpu to write the 512 bits at one time to device memory, thus it can be used for posting direct wqe. Add direct wqe enable switch and address mapping. Link: https://lore.kernel.org/r/20211207124901.42123-2-liangwenpeng@huawei.com Signed-off-by: Yixing Liu <liuyixing1@huawei.com> Signed-off-by: Wenpeng Liang <liangwenpeng@huawei.com> Signed-off-by: Jason Gunthorpe <jgg@nvidia.com>
99 lines
2.7 KiB
C
99 lines
2.7 KiB
C
/* SPDX-License-Identifier: ((GPL-2.0 WITH Linux-syscall-note) OR Linux-OpenIB) */
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/*
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* Copyright (c) 2016 Hisilicon Limited.
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*
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* This software is available to you under a choice of one of two
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* licenses. You may choose to be licensed under the terms of the GNU
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* General Public License (GPL) Version 2, available from the file
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* COPYING in the main directory of this source tree, or the
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* OpenIB.org BSD license below:
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*
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* Redistribution and use in source and binary forms, with or
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* without modification, are permitted provided that the following
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* conditions are met:
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*
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* - Redistributions of source code must retain the above
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* copyright notice, this list of conditions and the following
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* disclaimer.
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*
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* - Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials
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* provided with the distribution.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*/
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#ifndef HNS_ABI_USER_H
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#define HNS_ABI_USER_H
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#include <linux/types.h>
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struct hns_roce_ib_create_cq {
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__aligned_u64 buf_addr;
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__aligned_u64 db_addr;
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__u32 cqe_size;
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__u32 reserved;
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};
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enum hns_roce_cq_cap_flags {
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HNS_ROCE_CQ_FLAG_RECORD_DB = 1 << 0,
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};
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struct hns_roce_ib_create_cq_resp {
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__aligned_u64 cqn; /* Only 32 bits used, 64 for compat */
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__aligned_u64 cap_flags;
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};
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struct hns_roce_ib_create_srq {
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__aligned_u64 buf_addr;
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__aligned_u64 db_addr;
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__aligned_u64 que_addr;
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};
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struct hns_roce_ib_create_srq_resp {
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__u32 srqn;
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__u32 reserved;
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};
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struct hns_roce_ib_create_qp {
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__aligned_u64 buf_addr;
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__aligned_u64 db_addr;
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__u8 log_sq_bb_count;
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__u8 log_sq_stride;
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__u8 sq_no_prefetch;
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__u8 reserved[5];
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__aligned_u64 sdb_addr;
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};
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enum hns_roce_qp_cap_flags {
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HNS_ROCE_QP_CAP_RQ_RECORD_DB = 1 << 0,
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HNS_ROCE_QP_CAP_SQ_RECORD_DB = 1 << 1,
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HNS_ROCE_QP_CAP_OWNER_DB = 1 << 2,
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HNS_ROCE_QP_CAP_DIRECT_WQE = 1 << 5,
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};
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struct hns_roce_ib_create_qp_resp {
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__aligned_u64 cap_flags;
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__aligned_u64 dwqe_mmap_key;
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};
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struct hns_roce_ib_alloc_ucontext_resp {
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__u32 qp_tab_size;
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__u32 cqe_size;
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__u32 srq_tab_size;
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__u32 reserved;
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};
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struct hns_roce_ib_alloc_pd_resp {
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__u32 pdn;
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};
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#endif /* HNS_ABI_USER_H */
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