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621f48e40e
Currently external aborts are unsupported by the guest abort handling. Add handling for SEAs so that the host kernel reports SEAs which occur in the guest kernel. When an SEA occurs in the guest kernel, the guest exits and is routed to kvm_handle_guest_abort(). Prior to this patch, a print message of an unsupported FSC would be printed and nothing else would happen. With this patch, the code gets routed to the APEI handling of SEAs in the host kernel to report the SEA information. Signed-off-by: Tyler Baicar <tbaicar@codeaurora.org> Acked-by: Catalin Marinas <catalin.marinas@arm.com> Acked-by: Marc Zyngier <marc.zyngier@arm.com> Acked-by: Christoffer Dall <cdall@linaro.org> Signed-off-by: Will Deacon <will.deacon@arm.com>
252 lines
7.7 KiB
C
252 lines
7.7 KiB
C
/*
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* Copyright (C) 2012 - Virtual Open Systems and Columbia University
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* Author: Christoffer Dall <c.dall@virtualopensystems.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License, version 2, as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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*/
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#ifndef __ARM_KVM_ARM_H__
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#define __ARM_KVM_ARM_H__
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#include <linux/const.h>
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#include <linux/types.h>
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/* Hyp Configuration Register (HCR) bits */
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#define HCR_TGE (1 << 27)
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#define HCR_TVM (1 << 26)
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#define HCR_TTLB (1 << 25)
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#define HCR_TPU (1 << 24)
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#define HCR_TPC (1 << 23)
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#define HCR_TSW (1 << 22)
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#define HCR_TAC (1 << 21)
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#define HCR_TIDCP (1 << 20)
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#define HCR_TSC (1 << 19)
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#define HCR_TID3 (1 << 18)
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#define HCR_TID2 (1 << 17)
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#define HCR_TID1 (1 << 16)
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#define HCR_TID0 (1 << 15)
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#define HCR_TWE (1 << 14)
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#define HCR_TWI (1 << 13)
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#define HCR_DC (1 << 12)
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#define HCR_BSU (3 << 10)
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#define HCR_BSU_IS (1 << 10)
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#define HCR_FB (1 << 9)
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#define HCR_VA (1 << 8)
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#define HCR_VI (1 << 7)
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#define HCR_VF (1 << 6)
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#define HCR_AMO (1 << 5)
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#define HCR_IMO (1 << 4)
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#define HCR_FMO (1 << 3)
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#define HCR_PTW (1 << 2)
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#define HCR_SWIO (1 << 1)
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#define HCR_VM 1
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/*
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* The bits we set in HCR:
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* TAC: Trap ACTLR
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* TSC: Trap SMC
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* TVM: Trap VM ops (until MMU and caches are on)
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* TSW: Trap cache operations by set/way
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* TWI: Trap WFI
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* TWE: Trap WFE
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* TIDCP: Trap L2CTLR/L2ECTLR
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* BSU_IS: Upgrade barriers to the inner shareable domain
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* FB: Force broadcast of all maintainance operations
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* AMO: Override CPSR.A and enable signaling with VA
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* IMO: Override CPSR.I and enable signaling with VI
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* FMO: Override CPSR.F and enable signaling with VF
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* SWIO: Turn set/way invalidates into set/way clean+invalidate
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*/
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#define HCR_GUEST_MASK (HCR_TSC | HCR_TSW | HCR_TWI | HCR_VM | HCR_BSU_IS | \
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HCR_FB | HCR_TAC | HCR_AMO | HCR_IMO | HCR_FMO | \
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HCR_TVM | HCR_TWE | HCR_SWIO | HCR_TIDCP)
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/* System Control Register (SCTLR) bits */
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#define SCTLR_TE (1 << 30)
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#define SCTLR_EE (1 << 25)
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#define SCTLR_V (1 << 13)
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/* Hyp System Control Register (HSCTLR) bits */
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#define HSCTLR_TE (1 << 30)
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#define HSCTLR_EE (1 << 25)
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#define HSCTLR_FI (1 << 21)
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#define HSCTLR_WXN (1 << 19)
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#define HSCTLR_I (1 << 12)
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#define HSCTLR_C (1 << 2)
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#define HSCTLR_A (1 << 1)
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#define HSCTLR_M 1
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#define HSCTLR_MASK (HSCTLR_M | HSCTLR_A | HSCTLR_C | HSCTLR_I | \
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HSCTLR_WXN | HSCTLR_FI | HSCTLR_EE | HSCTLR_TE)
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/* TTBCR and HTCR Registers bits */
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#define TTBCR_EAE (1 << 31)
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#define TTBCR_IMP (1 << 30)
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#define TTBCR_SH1 (3 << 28)
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#define TTBCR_ORGN1 (3 << 26)
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#define TTBCR_IRGN1 (3 << 24)
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#define TTBCR_EPD1 (1 << 23)
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#define TTBCR_A1 (1 << 22)
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#define TTBCR_T1SZ (7 << 16)
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#define TTBCR_SH0 (3 << 12)
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#define TTBCR_ORGN0 (3 << 10)
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#define TTBCR_IRGN0 (3 << 8)
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#define TTBCR_EPD0 (1 << 7)
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#define TTBCR_T0SZ (7 << 0)
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#define HTCR_MASK (TTBCR_T0SZ | TTBCR_IRGN0 | TTBCR_ORGN0 | TTBCR_SH0)
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/* Hyp System Trap Register */
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#define HSTR_T(x) (1 << x)
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#define HSTR_TTEE (1 << 16)
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#define HSTR_TJDBX (1 << 17)
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/* Hyp Coprocessor Trap Register */
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#define HCPTR_TCP(x) (1 << x)
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#define HCPTR_TCP_MASK (0x3fff)
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#define HCPTR_TASE (1 << 15)
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#define HCPTR_TTA (1 << 20)
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#define HCPTR_TCPAC (1 << 31)
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/* Hyp Debug Configuration Register bits */
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#define HDCR_TDRA (1 << 11)
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#define HDCR_TDOSA (1 << 10)
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#define HDCR_TDA (1 << 9)
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#define HDCR_TDE (1 << 8)
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#define HDCR_HPME (1 << 7)
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#define HDCR_TPM (1 << 6)
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#define HDCR_TPMCR (1 << 5)
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#define HDCR_HPMN_MASK (0x1F)
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/*
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* The architecture supports 40-bit IPA as input to the 2nd stage translations
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* and PTRS_PER_S2_PGD becomes 1024, because each entry covers 1GB of address
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* space.
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*/
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#define KVM_PHYS_SHIFT (40)
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#define KVM_PHYS_SIZE (_AC(1, ULL) << KVM_PHYS_SHIFT)
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#define KVM_PHYS_MASK (KVM_PHYS_SIZE - _AC(1, ULL))
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#define PTRS_PER_S2_PGD (_AC(1, ULL) << (KVM_PHYS_SHIFT - 30))
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/* Virtualization Translation Control Register (VTCR) bits */
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#define VTCR_SH0 (3 << 12)
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#define VTCR_ORGN0 (3 << 10)
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#define VTCR_IRGN0 (3 << 8)
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#define VTCR_SL0 (3 << 6)
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#define VTCR_S (1 << 4)
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#define VTCR_T0SZ (0xf)
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#define VTCR_MASK (VTCR_SH0 | VTCR_ORGN0 | VTCR_IRGN0 | VTCR_SL0 | \
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VTCR_S | VTCR_T0SZ)
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#define VTCR_HTCR_SH (VTCR_SH0 | VTCR_ORGN0 | VTCR_IRGN0)
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#define VTCR_SL_L2 (0 << 6) /* Starting-level: 2 */
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#define VTCR_SL_L1 (1 << 6) /* Starting-level: 1 */
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#define KVM_VTCR_SL0 VTCR_SL_L1
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/* stage-2 input address range defined as 2^(32-T0SZ) */
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#define KVM_T0SZ (32 - KVM_PHYS_SHIFT)
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#define KVM_VTCR_T0SZ (KVM_T0SZ & VTCR_T0SZ)
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#define KVM_VTCR_S ((KVM_VTCR_T0SZ << 1) & VTCR_S)
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/* Virtualization Translation Table Base Register (VTTBR) bits */
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#if KVM_VTCR_SL0 == VTCR_SL_L2 /* see ARM DDI 0406C: B4-1720 */
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#define VTTBR_X (14 - KVM_T0SZ)
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#else
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#define VTTBR_X (5 - KVM_T0SZ)
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#endif
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#define VTTBR_BADDR_SHIFT (VTTBR_X - 1)
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#define VTTBR_BADDR_MASK (((_AC(1, ULL) << (40 - VTTBR_X)) - 1) << VTTBR_BADDR_SHIFT)
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#define VTTBR_VMID_SHIFT _AC(48, ULL)
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#define VTTBR_VMID_MASK(size) (_AT(u64, (1 << size) - 1) << VTTBR_VMID_SHIFT)
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/* Hyp Syndrome Register (HSR) bits */
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#define HSR_EC_SHIFT (26)
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#define HSR_EC (_AC(0x3f, UL) << HSR_EC_SHIFT)
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#define HSR_IL (_AC(1, UL) << 25)
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#define HSR_ISS (HSR_IL - 1)
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#define HSR_ISV_SHIFT (24)
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#define HSR_ISV (_AC(1, UL) << HSR_ISV_SHIFT)
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#define HSR_SRT_SHIFT (16)
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#define HSR_SRT_MASK (0xf << HSR_SRT_SHIFT)
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#define HSR_FSC (0x3f)
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#define HSR_FSC_TYPE (0x3c)
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#define HSR_SSE (1 << 21)
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#define HSR_WNR (1 << 6)
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#define HSR_CV_SHIFT (24)
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#define HSR_CV (_AC(1, UL) << HSR_CV_SHIFT)
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#define HSR_COND_SHIFT (20)
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#define HSR_COND (_AC(0xf, UL) << HSR_COND_SHIFT)
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#define FSC_FAULT (0x04)
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#define FSC_ACCESS (0x08)
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#define FSC_PERM (0x0c)
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#define FSC_SEA (0x10)
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#define FSC_SEA_TTW0 (0x14)
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#define FSC_SEA_TTW1 (0x15)
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#define FSC_SEA_TTW2 (0x16)
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#define FSC_SEA_TTW3 (0x17)
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#define FSC_SECC (0x18)
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#define FSC_SECC_TTW0 (0x1c)
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#define FSC_SECC_TTW1 (0x1d)
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#define FSC_SECC_TTW2 (0x1e)
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#define FSC_SECC_TTW3 (0x1f)
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/* Hyp Prefetch Fault Address Register (HPFAR/HDFAR) */
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#define HPFAR_MASK (~0xf)
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#define HSR_EC_UNKNOWN (0x00)
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#define HSR_EC_WFI (0x01)
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#define HSR_EC_CP15_32 (0x03)
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#define HSR_EC_CP15_64 (0x04)
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#define HSR_EC_CP14_MR (0x05)
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#define HSR_EC_CP14_LS (0x06)
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#define HSR_EC_CP_0_13 (0x07)
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#define HSR_EC_CP10_ID (0x08)
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#define HSR_EC_JAZELLE (0x09)
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#define HSR_EC_BXJ (0x0A)
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#define HSR_EC_CP14_64 (0x0C)
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#define HSR_EC_SVC_HYP (0x11)
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#define HSR_EC_HVC (0x12)
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#define HSR_EC_SMC (0x13)
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#define HSR_EC_IABT (0x20)
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#define HSR_EC_IABT_HYP (0x21)
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#define HSR_EC_DABT (0x24)
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#define HSR_EC_DABT_HYP (0x25)
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#define HSR_EC_MAX (0x3f)
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#define HSR_WFI_IS_WFE (_AC(1, UL) << 0)
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#define HSR_HVC_IMM_MASK ((_AC(1, UL) << 16) - 1)
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#define HSR_DABT_S1PTW (_AC(1, UL) << 7)
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#define HSR_DABT_CM (_AC(1, UL) << 8)
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#define HSR_DABT_EA (_AC(1, UL) << 9)
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#define kvm_arm_exception_type \
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{0, "RESET" }, \
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{1, "UNDEFINED" }, \
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{2, "SOFTWARE" }, \
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{3, "PREF_ABORT" }, \
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{4, "DATA_ABORT" }, \
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{5, "IRQ" }, \
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{6, "FIQ" }, \
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{7, "HVC" }
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#define HSRECN(x) { HSR_EC_##x, #x }
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#define kvm_arm_exception_class \
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HSRECN(UNKNOWN), HSRECN(WFI), HSRECN(CP15_32), HSRECN(CP15_64), \
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HSRECN(CP14_MR), HSRECN(CP14_LS), HSRECN(CP_0_13), HSRECN(CP10_ID), \
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HSRECN(JAZELLE), HSRECN(BXJ), HSRECN(CP14_64), HSRECN(SVC_HYP), \
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HSRECN(HVC), HSRECN(SMC), HSRECN(IABT), HSRECN(IABT_HYP), \
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HSRECN(DABT), HSRECN(DABT_HYP)
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#endif /* __ARM_KVM_ARM_H__ */
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